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Github doesn't render images unless absolute URL\n.. Do not know of a conditional tag, \"only: github\" nor \"github display\" works\n.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder\n.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0\n\n|badge1| |badge2| |badge3| |badge4| |badge5| |badge7| |badge8|\n\n.. |badge1| image:: https://img.shields.io/badge/Website-Verilator.org-181717.svg\n   :target: https://verilator.org\n.. |badge2| image:: https://img.shields.io/badge/License-LGPL%20v3-blue.svg\n   :target: https://www.gnu.org/licenses/lgpl-3.0\n.. |badge3| image:: https://img.shields.io/badge/License-Artistic%202.0-0298c3.svg\n   :target: https://opensource.org/licenses/Artistic-2.0\n.. |badge4| image:: https://repology.org/badge/tiny-repos/verilator.svg?header=distro%20packages\n   :target: https://repology.org/project/verilator/versions\n.. |badge5| image:: https://img.shields.io/docker/pulls/verilator/verilator\n   :target: https://hub.docker.com/r/verilator/verilator\n.. |badge7| image:: https://github.com/verilator/verilator/workflows/build/badge.svg\n   :target: https://github.com/verilator/verilator/actions?query=workflow%3Abuild\n.. |badge8| image:: https://img.shields.io/github/actions/workflow/status/verilator/verilator/rtlmeter.yml?branch=master\u0026event=schedule\u0026label=benchmarks\n   :target: https://verilator.github.io/verilator-rtlmeter-results\n\n\nWelcome to Verilator\n====================\n\n.. list-table::\n\n   * - **Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.**\n        * Accepts Verilog or SystemVerilog\n        * Performs lint code-quality checks\n        * Compiles into multithreaded C++, or SystemC\n        * Creates JSON to front-end your own tools\n     - |Logo|\n   * - |verilator multithreaded performance|\n     - **Fast**\n        * Outperforms many closed-source commercial simulators\n        * Single- and multithreaded output models\n   * - **Widely Used**\n        * Wide industry and academic deployment\n        * Out-of-the-box support from Arm and RISC-V vendor IP\n        * Over 700 contributors\n     - |verilator usage|\n   * - |verilator community|\n     - **Community Driven \u0026 Openly Licensed**\n        * Guided by the `CHIPS Alliance`_ and `Linux Foundation`_\n        * Open, and free as in both speech and beer\n        * More simulation for your verification budget\n   * - **Commercial Support Available**\n        * Commercial support contracts\n        * Design support contracts\n        * Enhancement contracts\n     - |verilator support|\n\n\nWhat Verilator Does\n===================\n\nVerilator is invoked with parameters similar to GCC or Synopsys's VCS. It\n\"Verilates\" the specified Verilog or SystemVerilog code by reading it,\nperforming lint checks, and optionally inserting assertion checks and\ncoverage-analysis points. It outputs single- or multithreaded .cpp and .h\nfiles, the \"Verilated\" code.\n\nVerilator can automatically generate a simulator executable (using\n``--binary``), or users can write their own C++/SystemC wrapper to\ninstantiate the model. The resulting Verilated executable performs the\ndesign simulation. Verilator also supports linking Verilator-generated\nlibraries, optionally encrypted, into other simulators.\n\nVerilator supports all design constructs, most verification constructs,\nintra-assignment delays (e.g, `#10`), and events. Tristate-bus (`z`) and\nunknowns (`x`) are handled in limited contexts, in a special manor for\nperformance. It currently may not be the best choice if you are expecting a\nfull-featured replacement for a closed-source Verilog simulator, performing\nSDF annotation, or mixed-signal simulation. However, if you are looking for\na path to migrate SystemVerilog to C++/SystemC, or want high-speed\nsimulation, Verilator is the tool for you.\n\n\nPerformance\n===========\n\nVerilator does not directly translate Verilog HDL to C++ or SystemC.\nRather, Verilator compiles your code into a much faster optimized and\noptionally thread-partitioned model, which is in turn wrapped inside a\nC++/SystemC module. The results are a compiled Verilog model that executes\neven on a single thread over 10x faster than standalone SystemC, and on a\nsingle thread is about 100 times faster than interpreted Verilog simulators\nsuch as `Icarus Verilog`_. Another 2-10x speedup might be gained from\nmultithreading (yielding 200-1000x total over interpreted simulators).\n\nVerilator has typically similar or better performance versus closed-source\nVerilog simulators (e.g., Aldec Riviera-Pro, Cadence Incisive/NC-Verilog,\nMentor ModelSim/Questa, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But,\nVerilator is open-sourced, so you can spend on computes rather than\nlicenses. Thus, Verilator gives you the best simulation cycles/dollar.\n\n\nInstallation \u0026 Documentation\n============================\n\nFor more information:\n\n- `Verilator installation and package directory structure\n  \u003chttps://verilator.org/install\u003e`_\n\n- `Verilator manual (HTML) \u003chttps://verilator.org/verilator_doc.html\u003e`_, or\n  `Verilator manual (PDF) \u003chttps://verilator.org/verilator_doc.pdf\u003e`_\n\n- `Subscribe to Verilator announcements\n  \u003chttps://github.com/verilator/verilator-announce\u003e`_\n\n- `Verilator forum \u003chttps://verilator.org/forum\u003e`_\n\n- `Verilator issues \u003chttps://verilator.org/issues\u003e`_\n\n\nSupport\n=======\n\nVerilator is a community project, guided by the `CHIPS Alliance`_ under the\n`Linux Foundation`_.\n\nWe appreciate and welcome your contributions in whatever form; please see\n`Contributing to Verilator\n\u003chttps://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst\u003e`_.\nThanks to our `Contributors and Sponsors\n\u003chttps://verilator.org/guide/latest/contributors.html\u003e`_.\n\nVerilator also supports and encourages commercial support models and\norganizations; please see `Verilator Commercial Support\n\u003chttps://verilator.org/verilator_commercial_support\u003e`_.\n\n\nRelated Projects\n================\n\n- `Cocotb \u003chttps://www.cocotb.org/\u003e`_ - A coroutine-based cosimulation\n  library for writing testbenches in Python which officially supports\n  Verilator.\n\n- `GTKwave \u003chttps://gtkwave.sourceforge.net/\u003e`_ - Waveform viewer for\n  Verilator traces.\n\n- `Icarus Verilog`_ - Icarus is a highly-featured interpreted Verilog\n  simulator. If Verilator does not support your needs, perhaps Icarus may.\n\n- `Surfer \u003chttps://surfer-project.org/\u003e`_ - Web or offline waveform viewer\n  for Verilator traces.\n\n\nOpen License\n============\n\nVerilator is Copyright 2003-2026 by Wilson Snyder. (Report bugs to\n`Verilator Issues \u003chttps://verilator.org/issues\u003e`_.)\n\nVerilator is free software; you can redistribute it and/or modify it under\nthe terms of either the GNU Lesser General Public License Version 3 or the\nPerl Artistic License Version 2.0. See the documentation for more details.\n\n.. _chips alliance: https://chipsalliance.org\n.. _icarus verilog: https://steveicarus.github.io/iverilog\n.. _linux foundation: https://www.linuxfoundation.org\n.. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png\n.. |verilator multithreaded performance| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png\n.. |verilator usage| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png\n.. |verilator community| image:: https://www.veripool.org/img/verilator_community_400x125-min.png\n.. |verilator support| image:: https://www.veripool.org/img/verilator_support_400x125-min.png\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fverilator%2Fverilator","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fverilator%2Fverilator","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fverilator%2Fverilator/lists"}