{"id":50446693,"url":"https://github.com/verilean/sparkle","last_synced_at":"2026-05-31T22:00:45.521Z","repository":{"id":332886228,"uuid":"1135339607","full_name":"Verilean/sparkle","owner":"Verilean","description":"A type-safe, formally verifiable HDL compiler in Lean 4. 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Prove it correct. Generate Verilog.**\n\nA type-safe hardware description language that brings dependent types and\ntheorem proving to hardware design.\n\n**Quick Start:** the multi-chapter [tutorial](docs/tutorial/) walks\nfrom \"hello counter\" through Verilog generation, proofs, and FPGA\nbring-up.  Run it in Docker, or read the rendered notebooks\ndirectly on GitHub.  For the full Signal DSL syntax, see\n[docs/reference/SignalDSL_Syntax.md](docs/reference/SignalDSL_Syntax.md).\n\n## The Sparkle Way: Verification-Driven Design\n\n1. **Write a pure Lean spec** — define behaviour as pure functions.\n2. **Prove properties** — safety, liveness, fairness via Lean's theorem prover.\n3. **Implement via Signal DSL** — express the same logic using `Signal`\n   combinators.\n4. **Generate Verilog** — `#synthesizeVerilog` / `#writeVerilogDesign` emit\n   SystemVerilog.\n\nSee [docs/reference/Verification_Framework.md](docs/reference/Verification_Framework.md) for\npatterns and a worked Round-Robin Arbiter example (10 formal proofs).\n\n## IP Catalog\n\nSparkle ships with production-grade IP cores — each with pure Lean specs,\nformal proofs, and synthesizable Signal DSL implementations.\n\n| IP | Description | Proofs | Synth | Details |\n|----|-------------|:------:|:-----:|---------|\n| [**BitNet b1.58**](docs/ip-catalog/BitNet.md) | Formally verified LLM inference accelerator. Ternary weights, Q16.16 datapath, dual architecture (1-cycle vs 12-cycle) | 60+ theorems | Full | 202K / 99K cells |\n| [**YOLOv8n-WorldV2**](docs/ip-catalog/YOLOv8.md) | Open-vocabulary object detection. INT4/INT8 quantized, 15 modules, CLIP text embeddings | Golden validation | Full | Backbone + Neck + Head |\n| [**RV32IMA SoC**](docs/ip-catalog/RV32.md) | RISC-V CPU — boots Linux 6.6.0. 4-stage pipeline, Sv32 MMU, UART, CLINT. JIT at 14.2M cyc/s (1.63x Verilator). 102 formal proofs | 102 theorems | Full | 122 registers |\n| [**AXI4-Lite Bus**](docs/ip-catalog/RV32.md) | Verified AXI4-Lite slave/master. Protocol compliance (valid persistence, deadlock-free), synthesizable | 14 theorems | Full | 23 sim tests |\n| [**SV→Sparkle Transpiler**](docs/ip-catalog/RV32.md#sv-transpiler) | Parse Verilog → JIT simulation. LiteX SoC at 18.1M cyc/s (1.72x Verilator). Verified reverse synthesis (2.14x speedup, zero sorry). 8-core parallel 11.9x Verilator. Timer oracle 9,900x. `OracleReduction` type class, 44 tests | 20+ theorems | JIT | 44 tests |\n| [**H.264 Codec**](docs/ip-catalog/H264.md) | Baseline Profile encoder + decoder. Hardware MP4 muxer produces playable files. 14 modules | 15+ theorems | Full | 709-byte MP4 output |\n| [**CDC Infrastructure**](docs/architecture/CDC.md) | Lock-free multi-clock simulation. SPSC queue (210M ops/sec), rollback, 8-core parallel runner (3.87x speedup). JIT.runCDC | 12 theorems | C++ | N-thread parallel |\n\n---\n\n## Why Sparkle?\n\n```lean\n-- Write this in Lean...\ndef counter {dom : DomainConfig} : Signal dom (BitVec 8) :=\n  Signal.circuit do\n    let count ← Signal.reg 0#8\n    count \u003c~ count + 1#8\n    return count\n\n#synthesizeVerilog counter\n```\n\n```systemverilog\n// ...and get this Verilog\nmodule counter (\n    input  logic clk,\n    input  logic rst,\n    output logic [7:0] out\n);\n    logic [7:0] count;\n\n    always_ff @(posedge clk) begin\n        if (rst)\n            count \u003c= 8'h00;\n        else\n            count \u003c= count + 8'h01;\n    end\n\n    assign out = count;\nendmodule\n```\n\n**Three powerful ideas in one language:**\n\n1. **Simulate** — cycle-accurate functional simulation with pure Lean functions.\n2. **Synthesize** — automatic compilation to clean, synthesizable SystemVerilog.\n3. **Verify** — formal correctness proofs using Lean's theorem prover.\n\n## The Sparkle Advantage: Logical AND Physical Safety\n\nChisel + FIRRTL solve many *logical* hardware bugs (latches, comb loops) but\nleave you fighting timing-closure with external linters. Sparkle gives you\nboth out of the box:\n\n- **Logical Safety** — `Signal` enforces a strict DAG for combinational logic;\n  feedback is only possible through explicit `Signal.register` /\n  `Signal.loop`. Pattern-match exhaustiveness catches unhandled cases at\n  compile time. Unintended latches are impossible by construction.\n- **Physical / Timing Safety** — a built-in DRC pass (inspired by the STARC\n  guidelines) enforces registered outputs so Static Timing Analysis is\n  predictable and critical paths don't cross module boundaries.\n- **Readable Verilog** — Sparkle's IR keeps a 1:1 structural correspondence\n  with your Lean code. When the DRC flags a timing issue you can actually\n  read the generated SV to fix it.\n\n## Quick Start\n\n```bash\ngit clone https://github.com/Verilean/sparkle.git\ncd sparkle\nlake build                                # ~5 min first time\nlake env lean --run Examples/Counter.lean # smoke-test\n```\n\nA minimal register chain:\n\n```lean\nimport Sparkle\nopen Sparkle.Core.Domain\nopen Sparkle.Core.Signal\n\n-- Three-cycle delay line, polymorphic over clock domains.\ndef registerChain {dom : DomainConfig}\n    (input : Signal dom (BitVec 8)) : Signal dom (BitVec 8) :=\n  let d1 := Signal.register 0#8 input\n  let d2 := Signal.register 0#8 d1\n  Signal.register 0#8 d2\n\n#synthesizeVerilog registerChain\n```\n\nFor the full tour — VCD waveforms, JIT simulation, formal equivalence\ncommands, clock-domain crossings, and the synthesizable subset of Lean —\nwork through [`docs/tutorial/`](docs/tutorial/).\n\n## Key Features\n\n- **Cycle-accurate simulation** — the same semantics as the emitted Verilog,\n  runnable from Lean with `#eval` and `sample`.\n- **Automatic Verilog generation** — `#synthesizeVerilog` handles clocks,\n  resets, register inference, bit-width checking, and feedback-loop\n  resolution.\n- **Formal verification ready** — `bv_decide` + `simp` + `Temporal.lean`\n  (LTL) for safety/liveness/fairness proofs directly against Signal code.\n- **One-line equivalence checks** — `#verify_eq`, `#verify_eq_at`,\n  `#verify_eq_git` auto-generate theorems and discharge them with\n  `bv_decide`. See `docs/tutorial/notebooks/ch07-equivalence.ipynb`.\n- **Signal DSL with imperative feel** — `Signal.circuit` macro gives you\n  `\u003c~` register assignment without losing the functional semantics.\n- **Vector / array types** — `HWVector α n` with compile-time-checked\n  indexing for register files.\n- **Memory primitives** — `Signal.memory` generates synchronous-write /\n  registered-read BRAM-style RAMs.\n- **Technology library support** — `primitiveModule` wraps vendor cells\n  (SRAMs, PLLs, transceivers) into the type system.\n- **JIT simulation** — `sim!` / `#sim` compile to native C++ via dlopen\n  for 10–100× faster simulation than the Lean interpreter.\n- **CDC-aware multi-domain simulation** — `runSim` auto-selects the fastest\n  backend (single-domain or lock-free SPSC queue between threads).\n- **Temporal logic** — LTL operators (`always`, `eventually`, `next`,\n  `Until`) with induction principles, enabling cycle-skipping optimisation.\n\nEach feature is exercised in the tutorial or one of the IPs; see the\nlinks in the IP Catalog above.\n\n## Examples\n\n```bash\n# Core simulation + Verilog generation\nlake env lean --run Examples/Counter.lean\nlake env lean --run Examples/LoopSynthesis.lean\nlake env lean --run Examples/SimpleMemory.lean\n\n# The 16-bit Sparkle-16 CPU (ALU / RegisterFile / Core / ISA proofs)\nlake env lean --run Examples/Sparkle16/Core.lean\nlake env lean --run Examples/Sparkle16/ISAProofTests.lean\n\n# Clock-domain crossing demo\nlake env lean --run Examples/CDC/MultiClockSim.lean\n\n# RV32IMA SoC, BitNet, YOLOv8, H.264 — run via the test suite\nlake test\n\n# Verilator: build the SoC and boot firmware\ncd verilator \u0026\u0026 make build \u0026\u0026 ./obj_dir/Vrv32i_soc ../firmware/firmware.hex 500000\n```\n\nEach IP has a dedicated getting-started recipe in its own doc\n([BitNet](docs/ip-catalog/BitNet.md), [RV32](docs/ip-catalog/RV32.md), [H264](docs/ip-catalog/H264.md),\n[YOLOv8](docs/ip-catalog/YOLOv8.md), [CDC](docs/architecture/CDC.md)).\n\n## Documentation\n\nGenerate the full API reference locally with doc-gen4:\n\n```bash\nlake -R -Kenv=dev build Sparkle:docs\nopen .lake/build/doc/index.html\n```\n\nPointers to the hand-written docs:\n\n- **Getting started / writing synthesizable code**\n  - [docs/tutorial/](docs/tutorial/) — multi-chapter beginner course\n  - [docs/reference/SignalDSL_Syntax.md](docs/reference/SignalDSL_Syntax.md) — full DSL reference\n  - [docs/reference/Troubleshooting_Synthesis.md](docs/reference/Troubleshooting_Synthesis.md)\n- **Verification**\n  - [docs/reference/Verification_Framework.md](docs/reference/Verification_Framework.md) — VDD patterns\n  - [Examples/TemporalLogicExample.md](Examples/TemporalLogicExample.md) — LTL usage\n- **IP-specific docs**\n  - [docs/ip-catalog/BitNet.md](docs/ip-catalog/BitNet.md) · [docs/ip-catalog/YOLOv8.md](docs/ip-catalog/YOLOv8.md)\n  - [docs/ip-catalog/RV32.md](docs/ip-catalog/RV32.md) · [docs/ip-catalog/H264.md](docs/ip-catalog/H264.md)\n  - [docs/architecture/CDC.md](docs/architecture/CDC.md)\n- **Project meta**\n  - [docs/CHANGELOG.md](docs/CHANGELOG.md) — release history\n  - [docs/architecture/STATUS.md](docs/architecture/STATUS.md) — current capability matrix\n  - [docs/known-issues/KnownIssues.md](docs/known-issues/KnownIssues.md)\n  - [docs/known-issues/BENCHMARK.md](docs/known-issues/BENCHMARK.md)\n\n## How It Works\n\n```\n┌──────────────────┐\n│  Lean Signal DSL │   ===, \u0026\u0026\u0026, |||, hw_cond, Coe\n└──────┬───────────┘\n       │\n       ├──────────────┬──────────────────┬───────────────────┐\n       ▼              ▼                  ▼                   ▼\n┌─────────────┐ ┌────────────┐  ┌──────────────┐ ┌──────────────────┐\n│ Simulation  │ │ JIT (FFI)  │  │  Verilator   │ │#synthesizeVerilog│\n│  .atTime t  │ │ C++ dlopen │  │ .sv → C++    │ │  Lean → IR → DRC │\n│  ~5K cyc/s  │ │ ~13.0M c/s │  │ ~11.1M c/s   │ │  → SystemVerilog │\n│             │ │+oracle:1B+ │  │              │ │                  │\n└─────────────┘ └────────────┘  └──────────────┘ └──────────────────┘\n```\n\n**Core abstractions:**\n\n1. **Domain** — clock domain configuration (period, edge, reset).\n2. **Signal** — stream-based hardware values, `Signal d α ≈ Nat → α`.\n3. **BitPack** — type class for hardware serialisation.\n4. **Module / Circuit** — IR for netlists.\n5. **Compiler** — automatic Lean → IR translation via metaprogramming.\n\nType-safety example:\n\n```lean\n-- This won't compile — bit-width mismatch is a compile-time error.\ndef broken {dom : DomainConfig} : Signal dom (BitVec 8) :=\n  Signal.register (0#16) (Signal.pure 0#16)  -- Error: expected BitVec 8\n\ndef fixed {dom : DomainConfig} : Signal dom (BitVec 8) :=\n  let wide : Signal dom (BitVec 16) := Signal.register 0#16 (Signal.pure 0#16)\n  wide.map (BitVec.extractLsb' 0 8 ·)  -- ✓ explicit truncation\n```\n\n## Known Limitations\n\nSee [docs/reference/Troubleshooting_Synthesis.md](docs/reference/Troubleshooting_Synthesis.md)\nand [docs/known-issues/KnownIssues.md](docs/known-issues/KnownIssues.md) for the current list of:\n\n- Imperative syntax limitations (`\u003c~` inside conditionals).\n- Pattern matching on tuples in synthesizable contexts.\n- `if`-then-else vs `Signal.mux` in Signal contexts.\n- `Signal.loop` feedback rules.\n- `bv_decide` hanging inside `lake build` on Lean 4.28 (interactive only).\n\n## Testing\n\n```bash\nlake test\n```\n\nRuns Signal simulation, Verilog generation, vector / memory ops, temporal\nlogic, CPU ISA proofs, BitNet golden-value validation, RV32 firmware,\nH.264 pipelines, YOLOv8 primitives, CDC queue stress, and the Verilator\nco-simulation layer.\n\n## Comparison with Other HDLs\n\n| Feature | Sparkle | Clash | Chisel | Verilog |\n|---------|---------|-------|--------|---------|\n| Language | Lean 4 | Haskell | Scala | Verilog |\n| Type System | Dependent Types | Strong | Strong | Weak |\n| Simulation | Built-in | Built-in | Built-in | External tools |\n| Formal Verification | **Native (Lean)** | External | External | None |\n| Logical Safety (no latches / comb loops) | **By construction** | Partial | Via FIRRTL | None |\n| Physical / Timing Safety (DRC) | **Built-in** | None | None | SpyGlass ($$$) |\n| Generated Verilog Readability | **1:1 structural** | Readable | Obfuscated (FIRRTL) | N/A |\n| Learning curve | High | High | Medium | Low |\n| Proof integration | **Seamless** | Separate | Separate | N/A |\n\n## Project Structure\n\n```\nsparkle/\n├── Sparkle/      # Core library (Signal DSL, IR, Compiler, Backend, Verification)\n├── IP/           # Verified IP cores (BitNet, YOLOv8, RV32, Drone, Humanoid, Video, Bus)\n├── Examples/     # Runnable demos (Counter, Sparkle16 CPU, CDC, LoopSynthesis, …)\n├── Tests/        # LSpec test suites for everything above\n├── Tools/        # SVParser, verilog! / sim! macros, Signal DSL helpers\n├── verilator/    # Verilator co-simulation backend for the RV32IMA SoC\n├── firmware/     # RV32 firmware + OpenSBI + Linux device tree\n├── c_src/        # C FFI libraries (loop memoization, JIT dlopen)\n├── scripts/      # Tutorial syntax check + golden-value generators\n├── docs/         # Hand-written docs (Tutorial, per-IP, KnownIssues, BENCHMARK)\n└── lakefile.lean # Build configuration\n```\n\n## Contributing\n\nSparkle is an educational project demonstrating functional hardware\ndescription, dependent types for hardware, theorem proving for\nverification, and compiler construction / metaprogramming.\n\nContributions welcome — good first areas:\n\n- Verified standard IP (parameterised FIFO, N-way arbiter, TileLink / AXI4\n  interconnect) with formal proofs.\n- FPGA tape-out flow examples.\n- Additional IR optimisation passes.\n- More tutorials and worked examples.\n\n## Roadmap\n\nCompleted phases live in [docs/CHANGELOG.md](docs/CHANGELOG.md).\n\n**Next up:**\n\n- **Verified Standard IP — Parameterised FIFO** — generic depth / width FIFO.\n- **Verified Standard IP — N-way Arbiter** — generalise the 2-client\n  round-robin arbiter to N clients.\n- **Verified Standard IP — TileLink / AXI4 Interconnect** — full AXI4\n  (bursts, IDs) and TileLink.\n- **GPGPU / Vector Core** — apply the VDD framework to highly concurrent,\n  memory-bound accelerator architectures.\n- **FPGA Tape-out Flow** — end-to-end examples deploying Sparkle-generated\n  Linux SoCs to physical FPGAs.\n\n## Author\n\n**Junji Hashimoto** — Twitter / X: [@junjihashimoto3](https://x.com/junjihashimoto3)\n\n## License\n\nApache License 2.0 — see [LICENSE](LICENSE).\n\n## Acknowledgments\n\n- Inspired by [Clash HDL](https://clash-lang.org/)\n- Built with [Lean 4](https://lean-lang.org/)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fverilean%2Fsparkle","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fverilean%2Fsparkle","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fverilean%2Fsparkle/lists"}