{"id":13831301,"url":"https://github.com/verilog-to-routing/tatum","last_synced_at":"2025-07-09T13:33:11.580Z","repository":{"id":42646645,"uuid":"41728934","full_name":"verilog-to-routing/tatum","owner":"verilog-to-routing","description":"Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits","archived":false,"fork":false,"pushed_at":"2024-05-28T20:17:41.000Z","size":2191,"stargazers_count":55,"open_issues_count":4,"forks_count":10,"subscribers_count":9,"default_branch":"master","last_synced_at":"2024-11-20T12:48:32.351Z","etag":null,"topics":["cad","eda","sta","tatum"],"latest_commit_sha":null,"homepage":"https://kmurray.github.io/tatum/","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/verilog-to-routing.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.txt","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2015-09-01T09:16:05.000Z","updated_at":"2024-10-19T17:27:44.000Z","dependencies_parsed_at":"2024-08-04T10:06:11.711Z","dependency_job_id":"8f5c1d66-1852-4af0-a842-d431f3078c64","html_url":"https://github.com/verilog-to-routing/tatum","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/verilog-to-routing/tatum","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/verilog-to-routing%2Ftatum","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/verilog-to-routing%2Ftatum/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/verilog-to-routing%2Ftatum/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/verilog-to-routing%2Ftatum/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/verilog-to-routing","download_url":"https://codeload.github.com/verilog-to-routing/tatum/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/verilog-to-routing%2Ftatum/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":264468166,"owners_count":23613045,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cad","eda","sta","tatum"],"created_at":"2024-08-04T10:01:24.078Z","updated_at":"2025-07-09T13:33:11.134Z","avatar_url":"https://github.com/verilog-to-routing.png","language":"C++","funding_links":[],"categories":["C++"],"sub_categories":[],"readme":"# Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits\n\n[![Build Status](https://travis-ci.org/kmurray/tatum.svg?branch=master)](https://travis-ci.org/kmurray/tatum)\n\n## Overview\nTatum is a block-based Static Timing Analysis (STA) engine suitable for integration with Computer-Aided Design (CAD) tools, which analyze, implement and optimize digital circuits.\nTatum supports both setup (max-delay) and hold (min-delay) analysis, clock skew, multiple clocks and a variety of timing exceptions.\n\nTatum is provided as a library (`libtatum`) which can be easily integrated into the host application.\nTatum operates on an abstract *timing graph* constructed by the host application, and can be configured to use an application defined delay calculator.\n\nTatum is optimized for high performance, as required by optimizing CAD tools.\nIn particular:\n  * Tatum performs only a *single* set of graph traversals to calculate timing information for all clocks and analyses (setup and hold).\n  * Tatum's data structures are cache optimized\n  * Tatum supports parallel analysis using multiple CPU cores\n\n## How to Cite\nIf your work uses Tatum please cite the following as a general citation:\n\nK. E. Murray and V. Betz, \"Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved Optimization\", *IEEE International Conference on Field-Programmable Technology (FPT)*, 2018\n\n**Bibtex:**\n```\n@inproceedings{c:tatum,\n    author = {Murray, Kevin E. and Betz, Vaughn},\n    title = {Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved Optimization},\n    booktitle = {IEEE International Conference on Field-Programmable Technology (FPT)},\n    year = {2018}\n}\n```\n\n## Documentation\nComming soon.\n\n## Download\nComming soon.\n\n## Projects using Tatum\n\nTatum is designed to be re-usable in a variety of appliations.\n\nSome of the known uses are:\n  * The [Verilog to Routing (VTR)](https://verilogtorouting.org) project for Field-Programmable Gate Array (FPGA) Architecture and CAD research. Tatum is used as the STA engine in the VPR placement and routing tool.\n  * The [CGRA-ME](http://cgra-me.ece.utoronto.ca/) framework for Coarse-Grained Reconfigurable Array (CGRA) Architecture research.\n\n*If your project is using Tatum please let us know!*\n\n## History\n\n### Why was Tatum created?\nI had need for a high performance, flexible STA engine for my research into FPGA architecture and CAD tools.\nI could find no suitable open source STA engines, and wrote my own.\n\n### Name Origin\nA *tatum* is a unit of time used in the computational analysis of music \\[[1]\\], named after Jazz pianist [Art Tatum](https://en.wikipedia.org/wiki/Art_Tatum).\n\n[1]: http://web.media.mit.edu/~tristan/phd/dissertation/chapter3.html#x1-390003.4.3\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fverilog-to-routing%2Ftatum","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fverilog-to-routing%2Ftatum","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fverilog-to-routing%2Ftatum/lists"}