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returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["hdl","rtl","rust","systemverilog","verilog"],"created_at":"2024-07-30T22:00:30.168Z","updated_at":"2026-03-04T10:05:16.860Z","avatar_url":"https://github.com/veryl-lang.png","language":"Rust","funding_links":["https://github.com/sponsors/dalance"],"categories":["Meta HDL and Transpilers","Rust","Circuit Compilers","⭐ Top Extensions"],"sub_categories":[],"readme":"[![Veryl](support/logo/veryl_wide.png)](https://veryl-lang.org/)\n\n[![Actions Status](https://github.com/veryl-lang/veryl/workflows/Regression/badge.svg)](https://github.com/veryl-lang/veryl/actions)\n[![Crates.io](https://img.shields.io/crates/v/veryl.svg)](https://crates.io/crates/veryl)\n[![CodSpeed Badge](https://img.shields.io/endpoint?url=https://codspeed.io/badge.json)](https://codspeed.io/veryl-lang/veryl)\n[![Docker Pulls](https://img.shields.io/docker/pulls/veryllang/veryl)](https://hub.docker.com/r/veryllang/veryl)\n[![DOI](https://zenodo.org/badge/575770340.svg)](https://zenodo.org/badge/latestdoi/575770340)\n\nVeryl is a modern hardware description language.\n\nThis project is under the exploration phase of language design.\nWe call for the following suggestion or contribution:\n\n* Language design\n* Tool implementation\n* Standard library implementation\n\nIf you have any idea, please open [Issue](https://github.com/veryl-lang/veryl/issues) or [Pull request](https://github.com/veryl-lang/veryl/pulls).\n\n## External resources\n\n* [Web Site](https://veryl-lang.org)\n* [Language Reference](https://doc.veryl-lang.org/book/)\n    * [日本語](https://doc.veryl-lang.org/book/ja/)\n* [PlayGround](https://doc.veryl-lang.org/playground/)\n* [Discord](https://discord.gg/MJZr9NufTT)\n\n## Documentation quick links\n\n* [Overview](#overview)\n* [Example](#example)\n* [FAQ](#faq)\n* [Installation \u0026 Usage](#installation--usage)\n* [Publications](#publications)\n* [Related Projects](#related-projects)\n* [License](#license)\n* [Contribution](#contribution)\n\n## Overview\n\nVeryl is a hardware description language based on SystemVerilog, providing the following advantages:\n\n### Optimized Syntax\nVeryl adopts syntax optimized for logic design while being based on a familiar basic syntax for SystemVerilog experts.\nThis optimization includes guarantees for synthesizability, ensuring consistency between simulation results, and providing numerous syntax simplifications for common idioms.\nThis approach enables ease of learning, improves the reliability and efficiency of the design process, and facilitates ease of code writing.\n\n### Interoperability\nDesigned with interoperability with SystemVerilog in mind, Veryl allows smooth integration and partial replacement with existing SystemVerilog components and projects.\nFurthermore, SystemVerilog source code transpiled from Veryl retains high readability, enabling seamless integration and debugging.\n\n### Productivity\nVeryl comes with a rich set of development support tools, including package managers, build tools, real-time checkers compatible with major editors such as VSCode, Vim, Emacs, automatic completion, and automatic formatting.\nThese tools accelerate the development process and significantly enhance productivity.\n\nWith these features, Veryl provides powerful support for designers to efficiently and productively conduct high-quality hardware design.\n\n## Example\n\n\u003ctable\u003e\n\u003ctr\u003e\n\u003cth\u003eVeryl\u003c/th\u003e\n\u003cth\u003eSystemVerilog\u003c/th\u003e\n\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\n\n```systemverilog\n/// documentation comment by markdown format\n/// * list item1\n/// * list item2\npub module Delay #( // visibility control by `pub` keyword\n    param WIDTH: u32 = 1, // trailing comma is allowed\n) (\n    i_clk : input  clock       ,\n    i_rst : input  reset       ,\n    i_data: input  logic\u003cWIDTH\u003e,\n    o_data: output logic\u003cWIDTH\u003e,\n) {\n    // unused variable which is not started with `_` are warned\n    var _unused_variable: logic;\n\n    // clock and reset signals can be omitted\n    // because Veryl can infer these signals\n    always_ff {\n        // abstraction syntax of reset polarity and synchronicity\n        if_reset {\n            o_data = '0;\n        } else {\n            o_data = i_data;\n        }\n    }\n}\n```\n\n\u003c/td\u003e\n\u003ctd\u003e\n\n```systemverilog\n// comment\n//\n//\nmodule Delay #(\n    parameter int WIDTH = 1\n) (\n    input              i_clk ,\n    input              i_rst ,\n    input  [WIDTH-1:0] i_data,\n    output [WIDTH-1:0] o_data\n);\n    logic unused_variable;\n\n    always_ff @ (posedge i_clk or negedge i_rst) begin\n        if (!i_rst) begin\n            o_data \u003c= '0;\n        end else begin\n            o_data \u003c= i_data;\n        end\n    end\nendmodule\n```\n\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/table\u003e\n\n## FAQ\n\n### Why not SystemVerilog?\n\nSystemVerilog is very complicated language, and it causes difficulty of implementing EDA tools for it.\nAs a consequence, major EDA tools only support SystemVerilog subset which is different each other,\nand users must explore usable languege features which are covered by adopted tools.\nAdditionally, the difficulty prevents productivity improvement by developing support tools.\nThis is a reason that a new language having simplified and sophisticated syntax, not SystemVerilog, is required.\n\n### Why not existing Alt-HDLs (e.g. Chisel)?\n\nMany existing alt-HDLs are inner DSL of a programming language.\nThis approach has some advantages like rapid development and resusable tooling ecosystem,\nbut the syntax can't be fit for hardware description completely.\nAdditionally, enormous Verilog code is generated from short and sophisticated code in these languages.\nThis prevents general ASIC workflows like timing improvement, pre/post-mask ECO because these workflows require FF-level modification in Verilog.\nInteropration between these language and SystemVerilog is challenging because these can't connect to SystemVerilog's type like `interface` and `struct` directly.\nBy these reason, the existing Alt-HDLs can't be used as alternative of SystemVerilog, especially if there are many existing SystemVerilog codebase.\nVeryl resolves these problems by HDL-specialized syntax and human-readable SystemVerilog code generation.\n\n### Why some language features (e.g. auto pipelining) are not adopted?\n\nVeryl focuses equivalency with SystemVerilog at the point of view of the language semantics.\nThis eases to predict the changes of generated SystemVerilog code from modification of Veryl code,\nand Veryl can be applied to ASIC workflows like timing improvement and pre/post-mask ECO.\nTherefore, some features generating FFs are not adopted because these prevent the predictability.\n\n### Why some syntax features (e.g. off-side rule, semicolon less) are not adopted?\n\nVeryl focuses syntax simplicity because it reduces tool implementation effort.\nTherefore syntax features which introduce large complexity in exchange for slight abbreviation are not adopted.\n\n### What is the origin of the name \"Veryl\"?\n\nVeryl derives its name from the first letter of Verilog and [\"Beryl\"](https://en.wikipedia.org/wiki/Beryl), and it is pronounced the same as beryl.\nThe theme color of Veryl comes from emerald, a type of beryl.\n\n## Installation \u0026 Usage\n\nSee [Getting Started](https://doc.veryl-lang.org/book/03_getting_started.html).\n\n## Publications\n\n* Naoya Hatta, Taichi Ishitani, Ryota Shioya.\n  Veryl: A New Hardware Description Language as an Alternative to SystemVerilog.\n  August 2024. In: The Design \u0026 Verification Conference (DVCon) Japan 2024.\n  [[Paper]](https://veryl-lang.org/docs/veryl_dvcon-jpn-2024.pdf)\n  [[Slides]](https://veryl-lang.org/docs/veryl_dvcon-jpn-2024-slide.pdf)\n  [[arXiv]](http://arxiv.org/abs/2411.12983)\n* Naoya Hatta.\n  Veryl: A New Hardware Description Language Developed as Open Source Software.\n  June 2025. In: 2025 Symposium on VLSI Technology and Circuits, Workshop 7 \"What is Possible with Open Chip Design? The Journey so Far.\".\n  [[Slides]](https://veryl-lang.org/docs/veryl_vlsi2025.pdf)\n* Naoya Hatta, Taichi Ishitani, Nathan Bleier.\n  Veryl: A Modern Hardware Description Language For Open Source Hardware Design.\n  June 2025. In: Open-Source Computer Architecture Research (OSCAR) co-located with ISCA 2025.\n  [[Slides]](https://veryl-lang.org/docs/veryl_oscar2025.pdf)\n* Naoya Hatta.\n  Veryl: SystemVerilogに代わる新しいハードウェア記述言語.\n  October 2025. In: Design Solution Forum 2025.\n  [[Slides]](https://veryl-lang.org/docs/veryl_dsf2025.pdf)\n\n## Related Projects\n\n* [RgGen](https://github.com/rggen/rggen)\n    * RgGen is an open source CSR automation tool.\n      It can generate CSR modules written in Veryl from readable register map specifications.\n\n## License\n\nLicensed under either of\n\n * Apache License, Version 2.0, ([LICENSE-APACHE](LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)\n * MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)\n\nat your option.\n\n### Contribution\n\nUnless you explicitly state otherwise, any contribution intentionally\nsubmitted for inclusion in the work by you, as defined in the Apache-2.0\nlicense, shall be dual licensed as above, without any additional terms or\nconditions.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fveryl-lang%2Fveryl","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fveryl-lang%2Fveryl","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fveryl-lang%2Fveryl/lists"}