{"id":23866031,"url":"https://github.com/vgalovic/hdl_examples","last_synced_at":"2026-02-14T21:30:59.836Z","repository":{"id":268598476,"uuid":"904876817","full_name":"vgalovic/HDL_examples","owner":"vgalovic","description":"A collection of VHDL and Verilog examples organized by language and modules, with setup.tcl files for easy Vivado setup. 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However, you are free to explore them in any order:\n\n1. **logic_gates** – Basic logic gates implementation\n1. **mux_demux** – Multiplexers and demultiplexers\n1. **coder_converter_comparator** – Encoders, decoders, converters, and comparators\n1. **latches_and_flip-flops** – Latches and flip-flops (sequential elements)\n1. **registers** – Register-based designs\n1. **memory** – Memory modules and related concepts\n1. **counters** – Various types of counters\n1. **FSM** – Finite State Machines\n1. **parameterized_design** – Parameterized modules and reusable components\n1. **hierarchical_design** – Hierarchical design with submodules\n\n\u003e 📝 **Note**:\n\u003e The _hierarchical_design_ module contains subprojects that demonstrate hierarchy in both `VHDL/` and `Verilog/`.\n\u003e You need to run the `setup.tcl` script separately for each subproject.\n\n## Getting Started\n\nTo get started with the examples, clone this repository to your local machine:\n\n```bash\ngit clone https://github.com/vgalovic/HDL_examples.git\n```\n\n## Setting Up the Vivado Project\n\nTo set up a specific module in _Vivado_, follow these steps:\n\n### 1. Fetch Latest Available Boards (if needed)\n\nIf you have just installed _Vivado_, you may need to fetch the latest available boards. Run the following command in the **TCL console**:\n\n```tcl\nxhub::refresh_catalog [xhub::get_xstores xilinx_board_store]\n```\n\n### 2. Source the Setup Script\n\nOnce the boards are updated, open the **TCL console** in _Vivado_ and run:\n\n```tcl\nsource \u003cbase_directory\u003e/HDL_examples/\u003clanguage\u003e/\u003cmodule\u003e/setup.tcl\n```\n\nThis will:\n\n- Create a new _Vivado_ project in:\n  - **Linux**: `$HOME/Documents/Vivado/HDL_examples/\u003clanguage\u003e/`\n  - **Windows**: `%USERPROFILE%\\Documents\\Vivado\\HDL_examples\\\u003clanguage\u003e\\`\n- Add all relevant source and simulation files for the selected module.\n- Set the top-level module/entity if it is specified in the `setup.tcl` script.\n\n\u003e **Replace** `\u003cbase_directory\u003e`, `\u003clanguage\u003e`, and `\u003cmodule\u003e` with the appropriate paths.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fvgalovic%2Fhdl_examples","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fvgalovic%2Fhdl_examples","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fvgalovic%2Fhdl_examples/lists"}