{"id":17279670,"url":"https://github.com/vlad-ivanov-name/verilog-zeroall","last_synced_at":"2025-03-26T14:46:08.741Z","repository":{"id":147684551,"uuid":"49337886","full_name":"vlad-ivanov-name/verilog-zeroall","owner":"vlad-ivanov-name","description":"Resets all register to zero in a Verilog design","archived":false,"fork":false,"pushed_at":"2016-01-09T19:22:31.000Z","size":3,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-01-31T16:15:43.013Z","etag":null,"topics":["modelsim","verilog"],"latest_commit_sha":null,"homepage":null,"language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/vlad-ivanov-name.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2016-01-09T19:20:22.000Z","updated_at":"2017-02-24T11:02:07.000Z","dependencies_parsed_at":"2023-04-17T23:32:58.746Z","dependency_job_id":null,"html_url":"https://github.com/vlad-ivanov-name/verilog-zeroall","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vlad-ivanov-name%2Fverilog-zeroall","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vlad-ivanov-name%2Fverilog-zeroall/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vlad-ivanov-name%2Fverilog-zeroall/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vlad-ivanov-name%2Fverilog-zeroall/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/vlad-ivanov-name","download_url":"https://codeload.github.com/vlad-ivanov-name/verilog-zeroall/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":245675606,"owners_count":20654424,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["modelsim","verilog"],"created_at":"2024-10-15T09:18:14.490Z","updated_at":"2025-03-26T14:46:08.722Z","avatar_url":"https://github.com/vlad-ivanov-name.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"## verilog-zeroall\n\nverilog-zeroall is a small library which uses VPI (Verilog Programming Interface) to provide a way to reset all signals in design to zero.\n\n### Why?\n\nMost FPGAs do not reset FFs/registers on power-up and require a dedicated reset path in code. However, there are some that reset all registers to zero on the event of POR. Therefore, the initial state of registers is not `X` but `0`. It is useful to have a system procedure that walks though the design hierarchy and resets all registers to `0`. The alternative is to specify an initial value for each `reg`.\n\n### Usage\n\nConnect the library to your simulator software and call `$zeroall` in your testbench:\n\n```verilog\nmodule tb();\n/* ... */\ninitial\n    $zeroall;\nendmodule;\n```\n\n### Building\n\n`premake` is used to build the library. You need to provide the following environment variables:\n\n* `PLI_INCLUDE_PATH`: path where `vpi_user.h` is located\n* `PLI_LIBRARY_PATH`: library path\n* `PLI_LIBRARY`: name of the library to link against\n\nConsult the manual of your simulator software to find out specific values.\n\n*Example: building the library for Active-HDL with GNU Make and mingw-32-gcc:*\n\n```\nPLI_INCLUDE_PATH='C:\\Software\\Aldec\\PLI\\Include' \\ \nPLI_LIBRARY_PATH='C:\\Software\\Aldec\\PLI\\Lib' \\ \nPLI_LIBRARY='aldecpli' \\\nGCC_PREFIX='i686-pc-mingw32-' \\ \npremake5 gmake\nmake\n```\n\n### Application-specific notes\n\nUse `reimp.exe` supplied with Active-HDL (`Aldec/MINGW/bin/reimp.exe`) to generate static library file if you want to build with GNU make and GCC.\n\n### Software support\n\nThe library should work with any IEEE 1364-2001 compatible simulator. The following combinations of compilers and simulators were tested:\n\nCompiler  | Simulator\n------------- | -------------\nmingw32-gcc  | Active-HDL 10.1\nVS2013  | Active-HDL 10.1\n\n### Why `vpiBinStrVal` instead of `vpiVectorVal`?\n\nApparently Modelsim/Questa does not support aval/bval representation of vectors.","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fvlad-ivanov-name%2Fverilog-zeroall","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fvlad-ivanov-name%2Fverilog-zeroall","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fvlad-ivanov-name%2Fverilog-zeroall/lists"}