{"id":13640218,"url":"https://github.com/vproc/vicuna","last_synced_at":"2025-04-20T02:32:58.941Z","repository":{"id":37462392,"uuid":"363177675","full_name":"vproc/vicuna","owner":"vproc","description":"RISC-V Zve32x Vector Coprocessor","archived":false,"fork":false,"pushed_at":"2023-12-02T15:07:37.000Z","size":783,"stargazers_count":152,"open_issues_count":34,"forks_count":45,"subscribers_count":6,"default_branch":"main","last_synced_at":"2024-08-03T01:16:28.391Z","etag":null,"topics":["coprocessor","risc-v","systemverilog","vector-processor"],"latest_commit_sha":null,"homepage":"","language":"Assembly","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/vproc.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.txt","code_of_conduct":null,"threat_model":null,"audit":null,"citation":"CITATION.cff","codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2021-04-30T15:10:31.000Z","updated_at":"2024-07-30T05:50:22.000Z","dependencies_parsed_at":"2024-01-14T09:09:02.365Z","dependency_job_id":"648b4190-f55e-4c5c-9abf-e880d8b83faa","html_url":"https://github.com/vproc/vicuna","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vproc%2Fvicuna","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vproc%2Fvicuna/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vproc%2Fvicuna/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vproc%2Fvicuna/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/vproc","download_url":"https://codeload.github.com/vproc/vicuna/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":223816483,"owners_count":17207868,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["coprocessor","risc-v","systemverilog","vector-processor"],"created_at":"2024-08-02T01:01:08.978Z","updated_at":"2024-11-09T10:30:59.854Z","avatar_url":"https://github.com/vproc.png","language":"Assembly","readme":"# Vicuna - a RISC-V Zve32x Vector Coprocessor\n\nVicuna is an open-source 32-bit integer vector coprocessor written in\nSystemVerilog that implements version 1.0 of the\n[RISC-V \"V\" Vector extension specification\n](https://github.com/riscv/riscv-v-spec).\nMore precisely, Vicuna complies with the `Zve32x` extension, a variant of the\n`V` extension aimed at embedded processors that do not require 64-bit elements\nor floating-point support (see Sect. 18.2 of the specification for details).\nAs such, Vicuna supports vector element widths of 8, 16, and 32 bits and\nimplements all vector load and store, vector integer[^1], vector fixed-point,\nvector integer reduction, vector mask, and vector permutation instructions.\n\n[^1]: Currently, the vector integer divide instructions (i.e., `vdiv`, `vdivu`,\n`vrem`, and `vremu`) are still missing.\n\nVicuna is a coprocessor and thus requires a main processor to function.  It\nuses the OpenHW Group's [CORE-V eXtension Interface\n](https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/) as interface\nto the main core.  Currently, a modified version of the [Ibex core\n](https://github.com/lowRISC/ibex) or the [CV32E40X core\n](https://github.com/openhwgroup/cv32e40x) serves as the main core.  Support\nfor further RISC-V CPUs is under development.\n\nVicuna is extensively configurable.  For instance, the width of the vector\nregisters, the number and layout of its execution pipelines and the width of\nits memory interface are configurable. The following figure gives a high-level\noverview of Vicuna.\n\n![Vicuna Overview Figure](docs/fig/vproc_overview.svg)\n\nVicuna is under active development, and contributions are welcome!\n\n\n## Documentation\n\nA high-level user guide for using Vicuna can be\n[read online at ReadTheDocs](http://vicuna.readthedocs.io/).\n\n\n## Publication\n\nIf you use Vicuna in academic work, please cite\n[our publication](https://doi.org/10.4230/LIPIcs.ECRTS.2021.1):\n\n```\n@InProceedings{platzer_et_al:LIPIcs.ECRTS.2021.1,\n  author =  {Platzer, Michael and Puschner, Peter},\n  title =   {{Vicuna: A Timing-Predictable RISC-V Vector Coprocessor for Scalable Parallel Computation}},\n  booktitle =   {33rd Euromicro Conference on Real-Time Systems (ECRTS 2021)},\n  pages =   {1:1--1:18},\n  series =  {Leibniz International Proceedings in Informatics (LIPIcs)},\n  ISBN =    {978-3-95977-192-4},\n  ISSN =    {1868-8969},\n  year =    {2021},\n  volume =  {196},\n  editor =  {Brandenburg, Bj\\\"{o}rn B.},\n  publisher =   {Schloss Dagstuhl -- Leibniz-Zentrum f{\\\"u}r Informatik},\n  address = {Dagstuhl, Germany},\n  URL =     {https://drops.dagstuhl.de/opus/volltexte/2021/13932},\n  URN =     {urn:nbn:de:0030-drops-139323},\n  doi =     {10.4230/LIPIcs.ECRTS.2021.1},\n  annote =  {Keywords: Real-time Systems, Vector Processors, RISC-V}\n}\n```\n\n\n## Getting Started\n\nThis repository uses submodules.  After cloning the repository, run following\ncommand in the top directory to initialize the submodules:\n```\ngit submodule update --init --recursive\n```\n\n### Compiling programs\n\nThe [`sw/`](https://github.com/vproc/vicuna/tree/main/sw) subdirectory\ncontains utilities for generating programs that can be executed on Vicuna.\n\n\n### Simulation\n\nThe [`sim/`](https://github.com/vproc/vicuna/tree/main/sim) subdirectory\ncontains scripts for simulating Vicuna with either\n[Verilator](https://www.veripool.org/verilator/), xsim (the default simulator\nin [Vivado](https://www.xilinx.com/products/design-tools/vivado.html)), or\nQuestasim.  For Verilator, version 4.210 or newer is required.\n\n\n### Synthesis\n\nThe [`demo/`](https://github.com/vproc/vicuna/tree/main/demo) subdirectory\ncontains a minimalist demo design for Xilinx FPGAs.\n\n\n## Configuration\n\nVicuna allows for extensive parametrization.  In particular, the width of\nthe vector registers, of the memory interface, and of the datapaths of the\nfunctional units can be configured independently.\n\n\n## License\n\nUnless otherwise noted, everything in this repository is licensed under the\n[Solderpad Hardware License v2.1](https://solderpad.org/licenses/SHL-2.1/), a\npermissive free software license that is based on the Apache-2.0 license.\n\nThe Ibex core (included in this repository as a submodule) is licensed under\nthe Apache License, see [the Ibex repository](https://github.com/lowRISC/ibex)\nfor details.\n\nThe CV32E40X core (included in this repository as a submodule) is licensed\nunder the Solderpad Hardware License, see\n[the CV32E40X repository](https://github.com/openhwgroup/cv32e40x) for details.\n","funding_links":[],"categories":["Assembly"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fvproc%2Fvicuna","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fvproc%2Fvicuna","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fvproc%2Fvicuna/lists"}