{"id":16359544,"url":"https://github.com/vygr/c-pcb","last_synced_at":"2025-03-16T15:32:23.469Z","repository":{"id":35069598,"uuid":"39214469","full_name":"vygr/C-PCB","owner":"vygr","description":"C++14 PCB autorouter","archived":false,"fork":false,"pushed_at":"2024-02-16T10:37:50.000Z","size":1791,"stargazers_count":75,"open_issues_count":11,"forks_count":17,"subscribers_count":11,"default_branch":"master","last_synced_at":"2024-10-12T02:08:58.279Z","etag":null,"topics":["c-plus-plus-14","dsn","pcb-layout"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/vygr.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2015-07-16T18:51:03.000Z","updated_at":"2024-09-15T13:55:01.000Z","dependencies_parsed_at":"2022-09-01T11:30:23.308Z","dependency_job_id":null,"html_url":"https://github.com/vygr/C-PCB","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vygr%2FC-PCB","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vygr%2FC-PCB/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vygr%2FC-PCB/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vygr%2FC-PCB/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/vygr","download_url":"https://codeload.github.com/vygr/C-PCB/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":221665531,"owners_count":16860275,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["c-plus-plus-14","dsn","pcb-layout"],"created_at":"2024-10-11T02:08:42.688Z","updated_at":"2024-10-27T10:51:03.304Z","avatar_url":"https://github.com/vygr.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"# C-PCB\n\n![](./test3.png)\n\n## C++14 PCB router and solver.\n\nRequires the glfw3 libs to be installed if you wish to build the viewer\napplication.\n\nBuild everything with:\n\n```\nmake -j\n```\n\nBuild just the parts you need with:\n\n```\nmake -j [c_pcb c_pcb_dsn c_pcb_view]\n```\n\nExample command lines would be:\n\n```\n./c_pcb --v 1 netlist.pcb | ./c_pcb_view --o 1 --s 7\n./c_pcb_dsn test1.dsn | ./c_pcb --v 2 --z 1 --q 4 --r 1 | ./c_pcb_view --s 12\n```\n\nYou can drop the output to a file and view it as an animation with:\n\n```\n./c_pcb --v 1 netlist.pcb \u003e anim\n./c_pcb_view anim\n```\n\n`-h` or `--help` for help on either app.\n\nFormat of .pcb input file or stdin follows, stdout format is identical:\n\n```\nDIMS : (double:width double:height double:depth)\nPOINT2D : (double:x double:y)\nPOINT3D : (double:x double:y double:z)\nSHAPE : (POINT2D ...)\nPATH : (POINT3D ...)\nPATHS : ([PATH ...])\nPAD : (double:pad_radius double:pad_gap POINT3D SHAPE)\nPADS : ([PAD ...])\nTRACK : (string:id double:track_radius double:via_radius double:track_gap PADS PATHS)\nPCB : DIMS TRACK ... ... ()\n```\n\nAny character before an opening ( will be ignored, so comments can be freely\nadded at any point the parser is looking for an opening (. Such comments are\nallowed in the input but will not be present in the output.\n\nAll track paths are assumed to have rounded ends and corners when testing for\ncollision gap clearance. If the resulting board is milled or etched with\nbeveled or square corners problems may occur in densely packed areas !\n\nAll the x, y, z co-ordinates of the board components MUST reside in the\nposative space ! Relative co-ordinates for SHAPE of pads will of course contain\nnegative members, but the resulting value once added to the PAD position MUST\nbe positive.\n\nSpecial treatment is given to tracks with a track_radius of 0.0, they are used\nto hold unused pads and keepout paths. No attempt is made to route them, they\nare just added to the collision hash for all other routing. PADS can be empty\nas well as PATHS.\n\nTracks containing paths as input to the router are treated as pre existing\nwiring and are preserved as is in the output. Only pads of tracks with no\nexisting wiring to them are routed.\n\n### DIMS : (double:width double:height double:depth)\n\nDimensions of the board in units and layers. depth is a double format but\nalways has a fractional part of 0.\n\neg.\n\n```\n(100.0 50.0 2.0)\n```\n\n### POINT2D : (double:x double:y)\n\n2D point in units.\n\neg.\n\n```\n(56.7 24.3)\n```\n\n### POINT3D : (double:x double:y double:z)\n\n3D point in units and layer. z layer is a double format but always has a\nfractional part of 0. Layers are numbered from 0.\n\neg.\n\n```\n(56.7 24.3 0.0)\n(50.7 25.3 1.0)\n```\n\n### SHAPE : (POINT2D ...)\n\n2D shape specified in relative units. These shapes are used to represent pad\npolygons, and are specified as closed polygons, the viewer fills these with a\nfan fill. An empty shape is used to signify a circular pad with radius of\npad_radius. Two points are used to indicate an oval pad using the two points\nand the pad_radius. 3 or more points are a polygon shape for the pad.\n\neg.\n\n```\ncircle -\u003e ()\noval -\u003e ((-20.0 0.0) (20.0 0.0))\nsquare -\u003e ((-5.0 -5.0) (-5.0 5.0) (5.0 5.0) (5.0 -5.0) (-5.0 -5.0))\n```\n\n### PATH : (POINT3D ...)\n\nA connected set of points on the PCB. Used to specify a section of a track or\nkeepout. Transitions between layers must only be vertical through the layers\nand signify a through via in that position. All vias are through vias, there\nare no blind vias.\n\neg.\n\n```\n((10.0 10.0 0.0) (20.0 5.0 0.0) (20.0 5.0 1.0) (30.0 10.0 1.0) (40.0 10.0 1.0))\n```\n\n### PATHS : ([PATH ...])\n\nA set of path sections electrically connected with each other, normally via the\npad terminals of components. Each track has a set of paths that are used to\ncreate the collision hash for that track. Paths data present in the input\nsignify existing pre wiring for this track or keepout, and is retain unchanged\nby the router while it fills in any remaining connections.\n\n### PAD : (double:pad_radius double:pad_gap POINT3D SHAPE)\n\nA single pad of a component. pads_radius is 0.0 if the pad shape is not a\ncircle or oval. pad_gap is the collision gap required by the pad in units. The\nPOINT3D is the position of the pad on the board and then the SHAPE is relative\nto that position.\n\n### PADS : ([PAD ...])\n\nRepresents all the electrically connected component pads of a track. A padstack\nshould be grouped together rather than being spread throughout the pads data.\nThis is because the router looks for a sequence of pads with matching x and y\nposition and uses the z min and max to create grid deformation information for\nneck down.\n\n### TRACK : (string:id double:track_radius double:via_radius double:track_gap PADS PATHS)\n\nA set of electrically connected component pads and paths, or unused pads and\nkeepouts. track_radius in units for the radius of all tracks, via_radius for\nthe radius of all vias within this track and track_gap for the required gap\nbetween the tracks and vias of this track any other components on the PCB.\ntrack_radius of 0.0 specifies unused pads and or keepouts.\n\nThe id is just a user supplied track identifier that is unchanged from the\ninput to output, as the order of tracks in the output may be changed due to the\nrouting process. This allows the identification or sorting of the output by the\noutput consumer process etc.\n\n## C_PCB options\n\n```\n-t:  timeout in seconds, default 600\n-v:  verbosity level 0..1, default 0\n-z:  vias cost, 0..100, default 0\n-s:  number of samples, default 1\n-r:  grid resolution 1..4, default 1\n-q:  area quantization, default 1\n-fr: flood range 1..5, default 2\n-xr: even layer x range 0..5, default 1\n-yr: odd layer y range 0..5, default 1\n```\n\n## More screenshots\n![](./test5.png)\n![](./test1.png)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fvygr%2Fc-pcb","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fvygr%2Fc-pcb","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fvygr%2Fc-pcb/lists"}