{"id":37020379,"url":"https://github.com/wiresynth/wiresynth-scala","last_synced_at":"2026-01-14T02:18:13.380Z","repository":{"id":308110843,"uuid":"1031700553","full_name":"wiresynth/wiresynth-scala","owner":"wiresynth","description":"Describing components and wiring in circuit board design with presentation in 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WireSynth.sc\n\nWireSynth.sc is DSL in Scala for describing components and wiring in circuit board design, which inspired by SpinalHDL.\nIt generates the final netlist for EDAs from presentation in Scala.\n\nWireSynth.sc aims to reduce the time cost of schematic design.\n\nThe major expense in circuit board design is in simulation, layout and signal integrity, but not schematic.\n\nSpending more time on PCB layout instead of drawing and dragging symbols in schematic editor.\n\nIt's recommended to use fonts with ligatures.\n\n## Project structure\n\nWireSynth.sc is still in active development and features are **unstable**.\n\n| Path        | Description                                              |\n|-------------|----------------------------------------------------------|\n| `core`      | DSL implementation.                                      |\n| `plugin`    | Scala 3 (Dotty) compiler plugin for marking DSL objects. |\n| `generator` | EDA-specified netlist generator.                         |\n\nBuilding DSL on a host language with full LSP support is more effective than launching another new language.\n\nThis is why I chose Scala.\n\n## Setup\n\n### sbt\n\nUse WireSynth.sc in your Scala project.\nYou have to add dependencies including a compiler plugin.\n\n`lib-kicad` contains parts and footprints authored by KiCad.\nThey are transformed into Scala source code.\n\n```scala\nlibraryDependencies ++= Seq(\n  \"io.github.wiresynth.sc\" %% \"core\" % coreVersion,\n  \"io.github.wiresynth.sc\" %% \"generator\" % coreVersion,\n  \"io.github.wiresynth.sc\" %% \"lib-kicad\" % \"0.9.1\",\n  compilerPlugin(\"io.github.wiresynth.sc\" %% \"plugin\" % coreVersion)\n)\n```\n\n## Overview\n\n#### Supported EDAs\n\n- [x] KiCad\n\n### Component\n\n`Component` is intermediary as virtual as module for design reusing.\nIt helps connect wires between different parts and nets.\n\n```scala\ncase class TopLevel() extends Component:\n  val Controller = STM32C011Jx()\n\n  val DC3v3 = BarrelJack()\n\n  DC3v3.P \u003c\u003e Controller.Vdd\n  DC3v3.G \u003c\u003e Controller.Vss\n```\n\n### Bundle\n\n`Bundle` is derived from `Component` but supports `\u003c\u003e` operator.\nIt can only accommodate pins.\n\n```scala\ncase class Differential() extends Bundle:\n  val P = Pin()\n  val N = Pin()\n\ncase class TopLevel() extends Component:\n  val A = Differential()\n  val B = Differential()\n  A \u003c\u003e B\n```\n\n### Part\n\n`Part` is derived from `Component` but it's marked as physical part.\nAny alive part and pin will be passed to final stage.\n\n```scala\ncase class STM32C011Jx() extends Part:\n  this packageIn kicad.Package_SO.SOIC_8_3p9x4p9mm_P1p27mm\n\n  val Vdd = Pin() @@ 2\n  val Gnd = Pin() @@ 3\n\n  val PA0_PA1_PA2_PF2 = Pin() @@ 4\n  val PA8_PA9_PA11 = Pin() @@ 5\n  val PA10_PA12 = Pin() @@ 6\n  val PA13 = Pin() @@ 7\n  val PA14_PB6_PC15 = Pin() @@ 8\n\n  val PB7_PC14 = Pin() @@ 1\n```\n\n### Pin \u003c\u003e Pin\n\n```scala\n// Net: { A, B, C, D }\nA \u003c\u003e B \u003c\u003e C \u003c\u003e D\n\n// Net: { A, B } ∪ { B, C, D }\nA \u003c\u003e B\nB \u003c\u003e C \u003c\u003e D\n```\n\n### Bundle \u003c\u003e Bundle\n\n```scala\ncase class Differential() extends Bundle:\n  val P = Pin()\n  val N = Pin()\n\ncase class TopLevel() extends Component:\n  val A = Differential()\n  val B = Differential()\n  A \u003c\u003e B\n```\n\n### Pin \u003c\u003e Neutral \u003c\u003e Pin\n\n```scala\n// Resistor\nMaster.P \u003c\u003e R(10 Ohm) \u003c\u003e Slave.P\nMaster.N \u003c\u003e R(10 Ohm) \u003c\u003e Slave.N\n\n// Inductor\nA \u003c\u003e L(4.7 uH) \u003c\u003e B\n\n// Capacitor\nP3v3 \u003c\u003e C(100 pF) \u003c\u003e Gnd\n// Equals\nval cap = C(100 pF)\ncap.A \u003c\u003e P3v3\ncap.B \u003c\u003e Gnd\n```\n\n### Pin -|+ Polarized |- Pin\n\n```scala\n// Capacitor\nP12v -|+ CP(47 uF) |- Gnd\n// Equals\nval cap = CP(47 uF)\n// -|+\ncap.P \u003c\u003e P12v\n// |-\ncap.N \u003c\u003e Gnd\n\n// Diode\nP3v3 \u003c\u003e R(12 Ohm) -|+ LED |- Gnd\n```\n\n## Elaboration\n\nAfter finishing designing the top level component, run elaboration and choose the target EDA for generating netlist.\n\n```scala\nKicad(Elaboration(TopLevel()), \"netlist.net\")\n```\n\nFinal netlist `netlist.net` will be generated in the working directory.\nImport it in *KiCad Pcbnew* and lay it out.\n\n## To do\n\n### Refinement\n\nCheck numeric range violation.\n\n### Schematic\n\nDraw schematic for single component.\n\n## Not planned\n\n### Pin direction\n\nThis feature is quite useless because the hierarchy of PCB is vague, and wires and nets in PCB design are not as strict as the digital circuits described in HDL.\n\nIn contrast to the clear hierarchy of SystemVerilog designs, copper board wiring does not necessarily follow a modular design.\n\n## Security\n\nDSL introduce programmability but also bring security risks from attackers.\nBe sure to conduct a security audit for third-party code.\n\n## License\n\nCopyright 2025 Jelly Terra \u003cjellyterra@proton.me\u003e\n\nUse of the source code is governed under the GNU Lesser General Public License version 2.1\n\nPlease share your improvements.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fwiresynth%2Fwiresynth-scala","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fwiresynth%2Fwiresynth-scala","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fwiresynth%2Fwiresynth-scala/lists"}