{"id":23122868,"url":"https://github.com/wissance/quickrs232","last_synced_at":"2026-03-20T00:41:09.804Z","repository":{"id":174016491,"uuid":"616615922","full_name":"Wissance/QuickRS232","owner":"Wissance","description":"A versatile full-duplex RS232 FPGA module with internal FIFO buffer on RX","archived":false,"fork":false,"pushed_at":"2024-08-06T19:06:02.000Z","size":757,"stargazers_count":2,"open_issues_count":7,"forks_count":0,"subscribers_count":3,"default_branch":"master","last_synced_at":"2025-04-04T04:24:42.463Z","etag":null,"topics":["altera-uart","fpga","fpga-programming","fpga-rs232","rs232","serial-communication","serial-communication-fpga","uart","uart-verilog","verilog-library","verilog-rs232","verilog-serial-port","verilog-uart"],"latest_commit_sha":null,"homepage":"https://wissance.github.io/QuickRS232/","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Wissance.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-03-20T18:29:52.000Z","updated_at":"2024-12-15T15:57:36.000Z","dependencies_parsed_at":null,"dependency_job_id":"f7f9e786-dc28-4176-a40a-94c5a60faf14","html_url":"https://github.com/Wissance/QuickRS232","commit_stats":null,"previous_names":["wissance/quickrs232"],"tags_count":4,"template":false,"template_full_name":null,"purl":"pkg:github/Wissance/QuickRS232","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Wissance%2FQuickRS232","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Wissance%2FQuickRS232/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Wissance%2FQuickRS232/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Wissance%2FQuickRS232/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Wissance","download_url":"https://codeload.github.com/Wissance/QuickRS232/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Wissance%2FQuickRS232/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28559350,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-19T00:46:33.223Z","status":"online","status_checked_at":"2026-01-19T02:00:08.049Z","response_time":67,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["altera-uart","fpga","fpga-programming","fpga-rs232","rs232","serial-communication","serial-communication-fpga","uart","uart-verilog","verilog-library","verilog-rs232","verilog-serial-port","verilog-uart"],"created_at":"2024-12-17T07:31:09.436Z","updated_at":"2026-01-19T03:01:48.108Z","avatar_url":"https://github.com/Wissance.png","language":"Verilog","readme":"## QuickRS232\n![GitHub code size in bytes](https://img.shields.io/github/languages/code-size/wissance/QuickRS232?style=plastic) \n![GitHub issues](https://img.shields.io/github/issues/wissance/QuickRS232?style=plastic)\n![GitHub Release Date](https://img.shields.io/github/release-date/wissance/QuickRS232?style=plastic)\n![GitHub release (latest by date)](https://img.shields.io/github/downloads/wissance/QuickRS232/v1.0/total?style=plastic)\n\n`QuickRS232` is a versatile `RS232` `FPGA` `Verilog` module with following features:\n* ***Internal data buffering*** with `FIFO` builtin in `RS232` with parametric `FIFO` depth;\n* ***Full-duplex mode*** (as `RS232` standard supports) with parallel Receive (`Rx`) and Transmit (`Tx`);\n* Supports ***either `No Flow Control` mode or Hardware Flow Control*** mode (`RTS + CTS`);\n\n`RS232` timing diagrams (`115200 bod/s`, `even parity`, `no flow control`):\n\n![RS232 Timing diagrams](/img/rs232_full_duplex_mode.png)\n\n`FIFO` timing diagrams\n\n![FIFO Timing diagrams](/img/fifo_diagrams.png)\n\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fwissance%2Fquickrs232","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fwissance%2Fquickrs232","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fwissance%2Fquickrs232/lists"}