{"id":15680793,"url":"https://github.com/woshiyyya/riscv-cpu","last_synced_at":"2026-01-07T23:08:08.395Z","repository":{"id":95353003,"uuid":"117053577","full_name":"woshiyyya/RISCV-CPU","owner":"woshiyyya","description":"Write a CPU from scratch!  (5-stage pipeline \u0026 2-way-cache)","archived":false,"fork":false,"pushed_at":"2019-07-18T17:56:51.000Z","size":1613,"stargazers_count":12,"open_issues_count":0,"forks_count":2,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-02-05T11:45:16.727Z","etag":null,"topics":["write"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/woshiyyya.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2018-01-11T05:17:36.000Z","updated_at":"2024-12-28T13:13:10.000Z","dependencies_parsed_at":null,"dependency_job_id":"c98f7748-3b2e-46fa-a6af-8da439653358","html_url":"https://github.com/woshiyyya/RISCV-CPU","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/woshiyyya%2FRISCV-CPU","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/woshiyyya%2FRISCV-CPU/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/woshiyyya%2FRISCV-CPU/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/woshiyyya%2FRISCV-CPU/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/woshiyyya","download_url":"https://codeload.github.com/woshiyyya/RISCV-CPU/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246301955,"owners_count":20755512,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["write"],"created_at":"2024-10-03T16:44:36.335Z","updated_at":"2026-01-07T23:08:08.368Z","avatar_url":"https://github.com/woshiyyya.png","language":"Verilog","readme":"# RISCV-CPU\nWrite a CPU with 5-stage Pipeline from scratch!\nComputer Architecture 2017-2018\n\n\n### Instruction List\n[cheat sheet](Instructions.pdf)\n```\nLUI AUIPC JAL JALR \nBEQ BNE BLT BGE BLTU BGEU \nLB LH LW LBU LHU \nSB SH SW \nADDI SLTI SLTIU XORI ORI ANDI SLLI SRLI SRAI \nADD SUB SLL SLT SLTU \nXOR SRL SRA OR AND \nFENCE FENCE.I\n```\n\n### CPU Architecture \n[Design.pdf](RISCV_CPU_Design.pdf)\n\n![](figure/arch.png)\n\n1. 增加了 EX、MA 两条 Forwarding 线，WB 阶段 Forwarding 由一个 Cycle 内寄存器先写后读实现，解决了除 Load/Store 之外的 RAW Harzard 问题。\n\n2. 内存采用哈佛结构，指令内存与数据内存分开，解决了数据与指令同时 访存的 Structual Hazard\n\n3. 实现了一个 data cache 模块， 内部由状态机控制时序， 采用块大小为 2MB(64*256bit) 的两路组关联 cache，LRU 替换策略\n\n4. 增加了流水线控制单元，监听 cache 模块 stall 信号以及 branch 指令跳 转信号，控制流水线暂停、清空、以及 PC 取指等操作。\n\n### D-Cache\n![](figure/d-cache.png)\n\n此设计为一级两路组关联 Cache，因此其命中率较高，大概有 80% 左右的 命中率，剩余 20% 情况均摊到 miss 或者 miss 且 dirty 的情况。\n\n我们使用的是 core 等待 cache 响应的机制，因此要提高 cpu 的速率，应考虑尽量缩短 core 对于 cache 进行访问的时间。\n\n为了便于控制 cache 与 core 和 memory 的交互，以及控制时序逻辑的需要, dcache 使用了如图所示的状态机控制内部功能模块。替换方式为 LRU，块大小为 256bits，保证了时间本地性与空间本地性。","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fwoshiyyya%2Friscv-cpu","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fwoshiyyya%2Friscv-cpu","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fwoshiyyya%2Friscv-cpu/lists"}