{"id":22661659,"url":"https://github.com/wpmed92/riscyd2","last_synced_at":"2025-04-12T06:11:40.787Z","repository":{"id":63241570,"uuid":"532900526","full_name":"wpmed92/RiscyD2","owner":"wpmed92","description":"A RISC-V based microcontroller","archived":false,"fork":false,"pushed_at":"2023-01-27T21:03:28.000Z","size":5207,"stargazers_count":8,"open_issues_count":0,"forks_count":0,"subscribers_count":3,"default_branch":"main","last_synced_at":"2025-04-12T06:11:31.910Z","etag":null,"topics":["cpu","hardware","microcontroller","python","riscv","verilog"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/wpmed92.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.md","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2022-09-05T12:54:42.000Z","updated_at":"2024-12-16T20:52:27.000Z","dependencies_parsed_at":"2023-02-15T12:46:04.130Z","dependency_job_id":null,"html_url":"https://github.com/wpmed92/RiscyD2","commit_stats":null,"previous_names":["softwiredtech/riscyd2","wpmed92/riscyd2"],"tags_count":2,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wpmed92%2FRiscyD2","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wpmed92%2FRiscyD2/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wpmed92%2FRiscyD2/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wpmed92%2FRiscyD2/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/wpmed92","download_url":"https://codeload.github.com/wpmed92/RiscyD2/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248525138,"owners_count":21118619,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpu","hardware","microcontroller","python","riscv","verilog"],"created_at":"2024-12-09T11:19:04.552Z","updated_at":"2025-04-12T06:11:40.766Z","avatar_url":"https://github.com/wpmed92.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"![RiscyD2](./demo/riscyd2_banner.png)\n\n---\n\nRiscyD2 is a tiny RISC-V based microcontroller/softcore running on a Digilent Arty A7-35T board.\n\n## Project structure\n\n- chip: RTL code for a RISC-V CPU core implementing the RV32I base instruction set, with M standard extension support.\n- binutils: Contains an assembler that emits RISC-V flat binary.\n- emulation: A RISC-V RV32IM emulator written in Python.\n- test: Simple unit tests for arithemtic, load/store and csr instructions.\n\nThe project is mainly educational, and is inspired by [From the Transistor to the Web Browser](https://github.com/geohot/fromthetransistor).\n\n## Prerequisites\n\n- Icarus Verilog\n- Python3\n- PySerial\n\n## Running on an FPGA\n\nRiscyD2 currently only supports Arty A7-35T, but the plan is to add support for more boards.\n\nTo set it up:\n- Compile the `bootrom`: \n\n`python3 binutils/asm/asm.py -i os/bootrom.asm -o code.o`\n\n- Save the `code.mem` file you got from the previous step\n- Create a Vivado project\n- Add the content of `chip/rtl` as design sources\n- Add `code.mem` as a Memory file\n- Add constraints located under `chip/fpga/arty_a7/arty_a7_35t.xdc` as constraint file\n- Synthesize, implement and generate bitstream\n- Load the bitstream to the board\n\nAt this point the chip is deployed to the board, and the `bootrom` is running. It continously checks the UART port for incoming exe files.\n\n## Programming RiscyD2\n\nTo compile programs for the board you can either use the assembler in the repository (recommended to run the programs in the `sample` folder), or use a real compiler, like [GCC](https://github.com/riscv-collab/riscv-gnu-toolchain).\n\n### Toy examples\n\nCompile an example program located under `sample`:\n\n`python3 binutils/asm/asm.py -i sample/switches.asm -o exe.o`\n\n### Real-world examples\n\nFor a relatively complex example program, see the [porting](https://github.com/wpmed92/TinyMaix-RiscyD2) of [TinyMaix](https://github.com/sipeed/TinyMaix) to RiscyD2.\n\nTo compile C programs, the following toolchain is recommended:\n\n- [GCC](https://github.com/riscv-collab/riscv-gnu-toolchain)\n- [Picolibc](https://github.com/picolibc/picolibc)\n- [riscyd2.h](lib/riscyd2.h)\n- [riscyd2.ld](lib/riscyd2.ld) (Picolibc linker script)\n\n\nSend the exe through UART:\n\n`python3 tools/talk2d2.py -i path/to/exe`\n\nThe binary format is fairly simple: the first 4 bytes encode the size of the exe, followed by the exe. That's it.\n\nTo listen to incoming data from the board, run:\n\n`python3 tools/listen2d2.py`\n\n(NOTE: to get the ID of your board run `ls /dev/tty.*` in your terminal.)\n\n## License\n\nMIT\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fwpmed92%2Friscyd2","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fwpmed92%2Friscyd2","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fwpmed92%2Friscyd2/lists"}