{"id":13427743,"url":"https://github.com/wyvernSemi/riscV","last_synced_at":"2025-03-16T00:32:24.813Z","repository":{"id":59925458,"uuid":"387694296","full_name":"wyvernSemi/riscV","owner":"wyvernSemi","description":"Open source ISS and logic RISC-V 32 bit project","archived":false,"fork":false,"pushed_at":"2024-07-18T14:23:57.000Z","size":34465,"stargazers_count":32,"open_issues_count":0,"forks_count":13,"subscribers_count":8,"default_branch":"main","last_synced_at":"2024-09-02T03:59:34.650Z","etag":null,"topics":["32-bit","c-plus-plus","co-simulation","cpu-model","embedded-systems","fpga","iss","linux","processor","risc-processor","risc-v","soft-core","verilog"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/wyvernSemi.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-07-20T06:25:27.000Z","updated_at":"2024-08-15T03:45:33.000Z","dependencies_parsed_at":"2024-07-18T16:48:48.590Z","dependency_job_id":null,"html_url":"https://github.com/wyvernSemi/riscV","commit_stats":{"total_commits":177,"total_committers":2,"mean_commits":88.5,"dds":0.02259887005649719,"last_synced_commit":"62a6f234c1f2b755c96c172ddc512d616b7a089a"},"previous_names":[],"tags_count":3,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wyvernSemi%2FriscV","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wyvernSemi%2FriscV/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wyvernSemi%2FriscV/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wyvernSemi%2FriscV/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/wyvernSemi","download_url":"https://codeload.github.com/wyvernSemi/riscV/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":221631812,"owners_count":16855012,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["32-bit","c-plus-plus","co-simulation","cpu-model","embedded-systems","fpga","iss","linux","processor","risc-processor","risc-v","soft-core","verilog"],"created_at":"2024-07-31T01:00:39.675Z","updated_at":"2024-10-27T05:30:24.117Z","avatar_url":"https://github.com/wyvernSemi.png","language":"C++","readme":"# riscV\nAn open source Verilog  Softcore and C++ Instruction Set Simulator and logic RISC-V 32 bit project. The project is meant to be an informative and educational exercise in the contruction of processor models and logic implementations, using the RISC-V open-source architecture as a base, as a modern, relevant, processor architecture.\n\nThe project, at this time, limits itself to the 32 bit specifications, but the implementations are architected to be an expandable implementation that can mix and match the various RISC-V expansion specifications (see HDL/doc/manual.pdf and iss/doc/iss_manual.pdf).\n\n## HDL\n\n\u003cp align=\"center\"\u003e\n\u003cimg src=\"https://github.com/wyvernSemi/riscV/assets/21970031/2f990f74-3681-44f7-aab2-d425e8599b4d\" width=600\u003e\n\u003c/p\u003e\n\nThe Verilog Softcore has the following features\n\n*\tAll RV32I instructions implemented\n\t*\tConfigurable for RV32E\n\t*\tSingle HART\n*\tConfigurable Zicsr extensions\n\t* csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci, mret instructions implemented\n\t* Sub-set of all possible machine registers implemented (see manual)\n\t* cycle counts, timer and retired insructions counts readable via unprivileged registers\n\t* Timer and retired instruction counts removable via parameters to save area\n*\tConfigurable RV32M extension functionality\n\t* mul, mulh, mulhu, mulhsu, div, divu, rem and remu instructions implemented\n    * Configuarble for implied DSP multiplier inference and for repated operand optimisations\n*\tSeparate instruction and data memory interfaces (Harvard architecture)\n*\t5 deep pipeline architecture\n*\t1 cycle operations for all instructions except branch, jump and load\n\t*\tRegfile update bypass feedback employed\n*\tBranch instructions take 1 cycle when not branching, 4 when branching\n\t*\t‘never take’ branch prediction policy employed, with pipeline cancellation on branch\n\t*\tJump instruction takes 4 cycles\n*\tLoad instructions take a minimum of 3 cycles, plus any additional wait states\n*\tRegister file configurable between register or RAM based\n\t*\tdefaults to RAM based, using 2 × M10K RAM blocks\n\t*\tRegister based costs approximately 700ALMs (~1900 LEs)\n*\tExample simulation test bench provided\n\t*\tTargets ModelSim\n*\tExample FPGA target platform using the terasIC DE10-nano development board (employing the Intel Cyclone V 5CSEBA6U23I7 FPGA).\n\t*\tTargeting 100MHz clock operation\n\t*\t\u003c 1000 ALMs (~2600 LEs) when also employing Zicsr and RV32M extensions (RV32I implementation currently around 700 ALMs, ~1900 LEs).\n\n## ISS\n\u003cp align=\"center\"\u003e\n\u003cimg src=\"https://github.com/wyvernSemi/riscV/assets/21970031/61eb37df-3997-43bc-aaf7-9a63da63149c\" width=600\u003e\n\u003c/p\u003e\n\nThe ISS has the following features:\n\n*\tRV32I ISA model\n*\tSupport for RV32E via compile option\n*\tCSR instructions and registers\n*\tRV32G extensions\n\t*\tRV32M\n\t*\tRV32A\n\t*\tRV32F\n\t*\tRV32D\n*\tRV32C extensions\t\n*\tSingle HART\n*\tOnly Machine (M) privilege currently mode supported\n*\tTrap handling\n*\tCycle count and real-time clock\n*\tInterrupt handling\n*\tExternal interrupts\n*\tTimer interrupts\n*\tSoftware interrupts\n*\tBasic internal memory model (16KBytes)\n*\tExternal memory callback feature\n*\tExternal interrupt callback feature\n*\tDisassembler, both run-time and static\n*\tLoading of ELF programs to memory\n*\tCo-simulation support for connecting to a Verilog or mixed signal logic simulator\n*\tRemote gdb debug interface for connection to gdb/IDEs\n","funding_links":[],"categories":["Open Source implementations","Open Source Core Implementations"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FwyvernSemi%2FriscV","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FwyvernSemi%2FriscV","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FwyvernSemi%2FriscV/lists"}