{"id":25070982,"url":"https://github.com/wyvernsemi/mem_model","last_synced_at":"2026-01-08T08:16:37.965Z","repository":{"id":151407952,"uuid":"392000135","full_name":"wyvernSemi/mem_model","owner":"wyvernSemi","description":"High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model","archived":false,"fork":false,"pushed_at":"2024-11-20T10:42:50.000Z","size":2844,"stargazers_count":22,"open_issues_count":0,"forks_count":2,"subscribers_count":3,"default_branch":"main","last_synced_at":"2024-11-20T12:11:25.037Z","etag":null,"topics":["avalon","axi","cosimulation","dpi-c","ghdl","memory-model","nvc","pli","questasim","simulation","test-bench","verilator","verilog","verilog-components","verilog-testbenches","vhdl","vivado-simulator"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/wyvernSemi.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-08-02T15:25:23.000Z","updated_at":"2024-11-20T10:30:05.000Z","dependencies_parsed_at":"2024-10-22T14:37:14.447Z","dependency_job_id":null,"html_url":"https://github.com/wyvernSemi/mem_model","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wyvernSemi%2Fmem_model","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wyvernSemi%2Fmem_model/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wyvernSemi%2Fmem_model/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wyvernSemi%2Fmem_model/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/wyvernSemi","download_url":"https://codeload.github.com/wyvernSemi/mem_model/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":237554156,"owners_count":19328990,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["avalon","axi","cosimulation","dpi-c","ghdl","memory-model","nvc","pli","questasim","simulation","test-bench","verilator","verilog","verilog-components","verilog-testbenches","vhdl","vivado-simulator"],"created_at":"2025-02-06T21:39:50.257Z","updated_at":"2026-01-08T08:16:37.891Z","avatar_url":"https://github.com/wyvernSemi.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# High speed C/C++ based behavioural Verilog an VHDL co-simulation memory model \n\n\u003cp align=\"center\"\u003e\n\u003cimg src=\"https://github.com/user-attachments/assets/909dd373-976a-4d48-97ba-32c3c46f76df\" width=800\u003e\n\u003c/p\u003e\n\nThe mem_model component is a Verilog/VHDL simulation test component that allows for a very large memory address space without reserving large amounts of memory, defining large HDL arrays, or building a truncated memory map into a test bench which could be subject to change in the design. The model uses the simulators' programming interfaces to access a C model, pushing the majority of the functionality away from the simulator, making the test bench lightweight, and the memory accesses very fast in simulation compute time.\n\nA direct access API is also provided to allow any other PLI C/C++ code to transfer data directly, without the overhead of simulating bus transactions (see \u003ctt\u003esrc/mem.h\u003c/tt\u003e). Wrapper HDL is also provided to map the ports to an AXI subordinate interface (\u003ctt\u003emem_model_axi.v\u003c/tt\u003e and \u003ctt\u003emem_model_axi.vhd\u003c/tt\u003e). The default memory mapped slave port and burst ports are Altera Avalon bus compatible.\n\nBy default memory is uninitialised but, if compiled with \u003ctt\u003eMEM_ZERO_NEW_PAGES\u003c/tt\u003e defined, memory will be initialised with zeros. By default, the model is big endian, but this can be overridden by defining \u003ctt\u003eMEM_MODEL_DEFAULT_ENDIAN=1\u003c/tt\u003e.\n\nThe model's software can be compiled for supporting various HDL languages, with the default being Verilog and using the PLI programming interface. To compile for the VPI interface, \u003ctt\u003eMEM_MODEL_PLI_VPI\u003c/tt\u003e should be defined when compiling the \u003ctt\u003emem_model.c\u003c/tt\u003e code. When using VHDL then \u003ctt\u003eMEM_MODEL_VHDL\u003c/tt\u003e should be defined. If using the SystemVerilog model then \u003ctt\u003eMEM_MODEL_SV\u003c/tt\u003e should be defined. The model's code, when used with VProc, will also recognise the VProc definitions (\u003ctt\u003eVPROC_PLI_VPI\u003c/tt\u003e, \u003ctt\u003eVPROC_VHDL\u003c/tt\u003e, and \u003ctt\u003eVPROC_SV\u003c/tt\u003e) and if these are defined when compiling the code, then the \u003ctt\u003eMEM_MODEL_XXX\u003c/tt\u003e definitions do not need to be set which are needed only when compiling as a standalone model. If compiling as a stand alone model (i.e. not compiled with VProc) then \u003ctt\u003eMEM_MODEL_INTERNAL_PLI\u003c/tt\u003e must be defined to enable registration of PLI routines when compiling Verilog in Questa and Icarus.\n\nIf using Verilog or SystemVerilog models, then the \u003ctt\u003etx_byteenable\u003c/tt\u003e port is enabled by defining \u003ctt\u003eMEM_EN_TX_BYTEENABLE\u003c/tt\u003e when analysing either \u003ctt\u003emem_model.v\u003c/tt\u003e or \u003ctt\u003emem_model.sv\u003c/tt\u003e.\n\n## Summary of HDL files and minimum compile options for each simulator\n\n| Simulator          | HDL files                      | C compilation definitions                 |\n|:-------------------|:-------------------------------|:------------------------------------------|\n| *Questa Verilog*   | \u003ctt\u003emem_model_q.v\u003c/tt\u003e         | \u003ctt\u003e[-DMEM_MODEL_PLI_VPI]\u003c/tt\u003e \u003ctt\u003e[-DMEM_MODEL_INTERNAL_PLI]\u003c/tt\u003e |\n|                    | \u003ctt\u003emem_model.v\u003c/tt\u003e           |                                           |\n|                    | \u003ctt\u003e[mem_model_axi.v]\u003c/tt\u003e     |                                           |\n|                    |                                |                                           |\n| *Icarus Verilog*   | \u003ctt\u003emem_model_q.v\u003c/tt\u003e         | \u003ctt\u003e[-DICARUS -DMEM_MODEL_INTERNAL_PLI]\u003c/tt\u003e|\n|                    | \u003ctt\u003emem_model.v\u003c/tt\u003e           |                                           |\n|                    | \u003ctt\u003e[mem_model_axi.v]\u003c/tt\u003e     |                                           |\n|                    |                                |                                           |\n| *Verilator*        | \u003ctt\u003emem_model_q.v\u003c/tt\u003e         | \u003ctt\u003e-DMEM_MODEL_SV\u003c/tt\u003e                   |\n|                    | \u003ctt\u003emem_model.sv\u003c/tt\u003e          |                                           |\n|                    | \u003ctt\u003e[mem_model_axi.sv]\u003c/tt\u003e    |                                           |\n|                    |                                |                                           |\n| *Vivado xsim*      | \u003ctt\u003emem_model_q.v\u003c/tt\u003e         | \u003ctt\u003e-DMEM_MODEL_SV\u003c/tt\u003e                   |\n|                    | \u003ctt\u003emem_model.sv\u003c/tt\u003e          |                                           |\n|                    | \u003ctt\u003e[mem_model_axi.sv]\u003c/tt\u003e    |                                           |\n|                    |                                |                                           |\n| *Questa VHDL*      | \u003ctt\u003emem_model_pkg.vhd\u003c/tt\u003e     | \u003ctt\u003e-DMEM_MODEL_VHDL\u003c/tt\u003e                 |\n|                    | \u003ctt\u003emem_model_q.vhd\u003c/tt\u003e       |                                           |\n|                    | \u003ctt\u003emem_model.vhd\u003c/tt\u003e         |                                           |\n|                    | \u003ctt\u003e[mem_model_axi.vhd]\u003c/tt\u003e   |                                           |\n|                    |                                |                                           |\n| *NVC*              | \u003ctt\u003emem_model_pkg_nvc.vhd\u003c/tt\u003e | \u003ctt\u003e-DMEM_MODEL_VHDL\u003c/tt\u003e                 |\n|                    | \u003ctt\u003emem_model_q.vhd\u003c/tt\u003e       |                                           |\n|                    | \u003ctt\u003emem_model.vhd\u003c/tt\u003e         |                                           |\n|                    | \u003ctt\u003e[mem_model_axi.vhd]\u003c/tt\u003e   |                                           |\n|                    |                                |                                           |\n| *GHDL*             | \u003ctt\u003emem_model_pkg_ghdl.vhd\u003c/tt\u003e| \u003ctt\u003e-DMEM_MODEL_VHDL\u003c/tt\u003e                 |\n|                    | \u003ctt\u003emem_model_q.vhd\u003c/tt\u003e       |                                           |\n|                    | \u003ctt\u003emem_model.vhd\u003c/tt\u003e         |                                           |\n|                    | \u003ctt\u003e[mem_model_axi.vhd]\u003c/tt\u003e   |                                           |\n\nMore details can be found in the manual\u0026mdash;\u003ctt\u003edoc/mem_model_manual.pdf\u003c/tt\u003e.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fwyvernsemi%2Fmem_model","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fwyvernsemi%2Fmem_model","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fwyvernsemi%2Fmem_model/lists"}