{"id":25070998,"url":"https://github.com/wyvernsemi/vproc","last_synced_at":"2025-10-03T18:16:50.728Z","repository":{"id":52574201,"uuid":"69550177","full_name":"wyvernSemi/vproc","owner":"wyvernSemi","description":"Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments","archived":false,"fork":false,"pushed_at":"2024-04-22T10:37:06.000Z","size":7376,"stargazers_count":21,"open_issues_count":0,"forks_count":6,"subscribers_count":5,"default_branch":"master","last_synced_at":"2024-04-22T11:44:45.785Z","etag":null,"topics":["asic-verification","c","codesign","cosimulation","cpp","dpi","dpi-c","fpga","logic","logic-simulation","pli","processor","python","simulation-element","systemverilog","verification","verilog","vhdl","vhpidirect","vpi"],"latest_commit_sha":null,"homepage":"http://www.anita-simulators.org.uk/wyvernsemi","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/wyvernSemi.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2016-09-29T09:01:17.000Z","updated_at":"2024-04-24T15:35:23.560Z","dependencies_parsed_at":"2023-11-13T10:31:05.685Z","dependency_job_id":"75c84f62-b572-4380-bbfb-4de2669c45ba","html_url":"https://github.com/wyvernSemi/vproc","commit_stats":null,"previous_names":[],"tags_count":9,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wyvernSemi%2Fvproc","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wyvernSemi%2Fvproc/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wyvernSemi%2Fvproc/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/wyvernSemi%2Fvproc/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/wyvernSemi","download_url":"https://codeload.github.com/wyvernSemi/vproc/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248961186,"owners_count":21189991,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic-verification","c","codesign","cosimulation","cpp","dpi","dpi-c","fpga","logic","logic-simulation","pli","processor","python","simulation-element","systemverilog","verification","verilog","vhdl","vhpidirect","vpi"],"created_at":"2025-02-06T21:39:53.236Z","updated_at":"2025-10-03T18:16:45.678Z","avatar_url":"https://github.com/wyvernSemi.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"# VProc\nVirtual processor co-simulation and co-design element for Verilog and VHDL environment. \n\nAllows native C/C++ programs or Python scripts to co-simulate with Verilog, SystemVerilog or VHDL simulations, with a memory mapped read/write interface and support to model interrupts. This enables virtually limitless possibilities for control of a simulation from C/C++ or Python programs, running as if on the instantiated virtual processor in the logic simulation. User code could be as simple as linear test program to drive pattrens on the bus, software models of processors and other SoC components, or embedded software, amongst other things. The software running on the virtual processor can be debugged using such standard tools such as \u003ctt\u003egdb\u003c/tt\u003e and related IDE applications such as Eclipse.\n\nCurrently supported simulators:\n\n * Questa : Verilog with VPI, VHDL with FLI\n * Icarus : Verilog with VPI\n * Vivado Xsim : SystemVerilog with DPI-C\n * Verilator : SystemVerilog with DPI-C\n * NVC : VHDL with VHPIDIRECT\n * GHDL : VHDL with VHPIDIRECT\n\nMore information can be found in the documentation located in \u003ccode\u003edoc/VProc.pdf\u003c/code\u003e and related articles on virtual processors, co-simulation and VProc can be found \u003ca href=\"https://www.linkedin.com/pulse/vproc-virtual-processor-vip-simon-southwell-pjmpe\"\u003ehere\u003c/a\u003e and \u003ca href=\"https://www.linkedin.com/pulse/extending-power-logic-simulations-using-programming-part-southwell-1e\"\u003ehere\u003c/a\u003e to complement the information in the manual.\n\n\u003chr\u003e\n\n### VProc HDL component\nThe diagram below shows the VProc component that's instantiated in the HDL.\n\u003cp align=\"center\"\u003e\n\u003cimg src=\"https://github.com/wyvernSemi/vproc/assets/21970031/71f770ac-5c5f-401c-bab2-4e3f376dba65\" width=800\u003e\n\u003c/p\u003e\n\u003chr\u003e\n\n### VProc stack with Python\nThe diagram below shows the stack for node 0 from the HDL environment (Verilog in this diagram) through to the user code\u0026mdash;in this case, python. For the C/C++ environment, the stack tops out at \u003ctt\u003eVUserMain0()\u003c/tt\u003e as the user code entry point, with any additional user hiearchy on top of this.\n\u003cp align=\"center\"\u003e\n\u003cimg src=\"https://github.com/wyvernSemi/vproc/assets/21970031/523db26f-e23b-4f26-9019-6fe985c9cb62\" width=700\u003e\n\u003c/p\u003e\n\nCopyright \u0026copy; 2024 Simon Southwell. All rights reserved.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fwyvernsemi%2Fvproc","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fwyvernsemi%2Fvproc","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fwyvernsemi%2Fvproc/lists"}