{"id":22880792,"url":"https://github.com/xuantie-rv/zero_stage_boot","last_synced_at":"2026-02-11T07:18:49.694Z","repository":{"id":200886663,"uuid":"704399465","full_name":"XUANTIE-RV/zero_stage_boot","owner":"XUANTIE-RV","description":null,"archived":false,"fork":false,"pushed_at":"2025-07-17T03:08:13.000Z","size":83,"stargazers_count":15,"open_issues_count":0,"forks_count":17,"subscribers_count":6,"default_branch":"master","last_synced_at":"2025-08-02T21:22:52.724Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/XUANTIE-RV.png","metadata":{"files":{"readme":"README.adoc","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.txt","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2023-10-13T07:15:48.000Z","updated_at":"2025-07-17T03:08:17.000Z","dependencies_parsed_at":null,"dependency_job_id":"c0c871c0-0430-4f9a-833b-b95bed40fafc","html_url":"https://github.com/XUANTIE-RV/zero_stage_boot","commit_stats":null,"previous_names":["t-head-semi/zero_stage_boot","xuantie-rv/zero_stage_boot"],"tags_count":9,"template":false,"template_full_name":null,"purl":"pkg:github/XUANTIE-RV/zero_stage_boot","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/XUANTIE-RV%2Fzero_stage_boot","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/XUANTIE-RV%2Fzero_stage_boot/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/XUANTIE-RV%2Fzero_stage_boot/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/XUANTIE-RV%2Fzero_stage_boot/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/XUANTIE-RV","download_url":"https://codeload.github.com/XUANTIE-RV/zero_stage_boot/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/XUANTIE-RV%2Fzero_stage_boot/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29329492,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-11T06:13:03.264Z","status":"ssl_error","status_checked_at":"2026-02-11T06:12:55.843Z","response_time":97,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-12-13T17:27:16.152Z","updated_at":"2026-02-11T07:18:49.678Z","avatar_url":"https://github.com/XUANTIE-RV.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"= Introduction\n\nThe zero stage boot is the XuanTie processor init code before opensbi. Before zero_stage_boot, SoC vendors must prepare ddr_init and CPU reset procedures. All harts would get into zero_stage_boot together, and the first one would duty to relocate GOT \u0026 offset variable, and others wait. Every hart would init its CSRs by their CPUID versions separately, allowing different harts to work together, e.g., 4*c908 + 2*c910. You could compile standard opensbi and Linux kernel binaries from open-source repositories, all compatible with XuanTie processors. Here is the simple boot flow:\n\n....\n[Jtag gdbinit] -\u003e [zero_stage_boot] -\u003e [opensbi] -\u003e [Linux]\n\nopensbi: https://github.com/riscv-software-src/opensbi\nLinux:   https://kernel.org/\n....\n\nCompiling zero_stage_boot is very straightforward, requiring only a standard RISC-V GCC compiler:\n\nCROSS_COMPILE=riscv64-unknown-linux-gnu- make\n\nHowever, we strongly recommend using the released binaries for the FPGA bringup. Click the Releases button on the right to obtain pre-compiled binaries for zsb, OpenSBI, and Image (Linux). These binary files have undergone comprehensive testing prior to release and contain detailed and precise version information.\n\n - 64lp64  means running  lp64 ABI on 64-bit Hardware.\n\n - 32ilp32 means running ilp32 ABI on 32-bit Hardware.\n\n - 64ilp32 means running ilp32 ABI on 64-bit Hardware.\n\n - zsb means zero_stage_boot.\n\n - Linux-5.10 + opensbi-0.9 is for early customers.\n\n - Linux-6.6 + opensbi-1.3 is for current.\n\n - zsb-64lp64-xt is simply recompiled with a custom compiler; functionally, it is identical to zsb-64lp64.\n\nFor a rv64 processor, you can download zsb-64lp64.tar.gz + opensbi-1.3-64lp64.tar.gz + linux-6.6-64lp64.tar.gz and prepare your own DTS + gdbinit.\n\nThen, you can use Jtag to run FPGA Platform.\n\n= linux-6.6 opensbi-1.3 DTS Example\n\nThe XuanTie C9xx DTB provided to OpenSBI generic firmware will usually have\n\"thead,c900-clint\", \"thead,c900-plic\", compatible strings.\n\n....\n/dts-v1/;\n/ {\n\tmodel = \"Test Sample\";\n\tcompatible = \"test,sample\";\n\t#address-cells = \u003c2\u003e;\n\t#size-cells = \u003c2\u003e;\n\n\tmemory@60000000 {\n\t\tdevice_type = \"memory\";\n                Caution: Determine your own address here\n\t\treg = \u003c0x0 0x60000000 0x0 0x40000000\u003e;\n\t};\n\n\tcpus {\n\t\t#address-cells = \u003c1\u003e;\n\t\t#size-cells = \u003c0\u003e;\n\t\ttimebase-frequency = \u003c25000000\u003e;\n\t\tcpu@0 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = \u003c0\u003e;\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"riscv\";\n\t\t\triscv,isa = \"rv64imafdc_zicbom_svpbmt_sstc_sscofpmf\";\n\t\t\triscv,cbom-block-size = \u003c64\u003e;\n\t\t\tmmu-type = \"riscv,sv57\";\n\t\t\tcpu0_intc: interrupt-controller {\n\t\t\t\t#address-cells = \u003c0\u003e;\n\t\t\t\t#interrupt-cells = \u003c1\u003e;\n\t\t\t\tcompatible = \"riscv,cpu-intc\";\n\t\t\t\tinterrupt-controller;\n\t\t\t};\n\t\t};\n\t\tcpu@1 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = \u003c1\u003e;\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"riscv\";\n\t\t\triscv,isa = \"rv64imafdc_zicbom_svpbmt_sstc_sscofpmf\";\n\t\t\triscv,cbom-block-size = \u003c64\u003e;\n\t\t\tmmu-type = \"riscv,sv57\";\n\t\t\tcpu1_intc: interrupt-controller {\n\t\t\t\t#address-cells = \u003c0\u003e;\n\t\t\t\t#interrupt-cells = \u003c1\u003e;\n\t\t\t\tcompatible = \"riscv,cpu-intc\";\n\t\t\t\tinterrupt-controller;\n\t\t\t};\n\t\t};\n\t\tcpu@2 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = \u003c2\u003e;\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"riscv\";\n\t\t\triscv,isa = \"rv64imafdc_zicbom_svpbmt_sstc_sscofpmf\";\n\t\t\triscv,cbom-block-size = \u003c64\u003e;\n\t\t\tmmu-type = \"riscv,sv57\";\n\t\t\tcpu2_intc: interrupt-controller {\n\t\t\t\t#address-cells = \u003c0\u003e;\n\t\t\t\t#interrupt-cells = \u003c1\u003e;\n\t\t\t\tcompatible = \"riscv,cpu-intc\";\n\t\t\t\tinterrupt-controller;\n\t\t\t};\n\t\t};\n\t\tcpu@3 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = \u003c3\u003e;\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"riscv\";\n\t\t\triscv,isa = \"rv64imafdc_zicbom_svpbmt_sstc_sscofpmf\";\n\t\t\triscv,cbom-block-size = \u003c64\u003e;\n\t\t\tmmu-type = \"riscv,sv57\";\n\t\t\tcpu3_intc: interrupt-controller {\n\t\t\t\t#address-cells = \u003c0\u003e;\n\t\t\t\t#interrupt-cells = \u003c1\u003e;\n\t\t\t\tcompatible = \"riscv,cpu-intc\";\n\t\t\t\tinterrupt-controller;\n\t\t\t};\n\t\t};\n\t};\n\n\n\tsoc {\n\t\t#address-cells = \u003c2\u003e;\n\t\t#size-cells = \u003c2\u003e;\n\t\tcompatible = \"simple-bus\";\n\t\tdma-noncoherent;\n\t\tranges;\n\n\t\tclint0: clint@c000000 {\n\t\t\tcompatible = \"thead,c900-clint\";\n\t\t\tinterrupts-extended = \u003c\n\t\t\t\t\u0026cpu0_intc  3 \u0026cpu0_intc  7\n\t\t\t\t\u0026cpu1_intc  3 \u0026cpu1_intc  7\n\t\t\t\t\u0026cpu2_intc  3 \u0026cpu2_intc  7\n\t\t\t\t\u0026cpu3_intc  3 \u0026cpu3_intc  7\n\t\t\t\t\u003e;\n\t\t\treg = \u003c0x0 0x0c000000 0x0 0x04000000\u003e;\n                Caution: Determine your own address here\n\t\t\tclint,has-no-64bit-mmio;\n\t\t};\n\n\t\tintc: interrupt-controller@8000000 {\n\t\t\t#address-cells = \u003c0\u003e;\n\t\t\t#interrupt-cells = \u003c2\u003e;\n\t\t\tcompatible = \"thead,c900-plic\";\n\t\t\treg = \u003c0x0 0x08000000 0x0 0x04000000\u003e;\n                Caution: Determine your own address here\n\t\t\triscv,ndev = \u003c64\u003e;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts-extended = \u003c\n\t\t\t\t\u0026cpu0_intc  0xffffffff \u0026cpu0_intc  9\n\t\t\t\t\u0026cpu1_intc  0xffffffff \u0026cpu1_intc  9\n\t\t\t\t\u0026cpu2_intc  0xffffffff \u0026cpu2_intc  9\n\t\t\t\t\u0026cpu3_intc  0xffffffff \u0026cpu3_intc  9\n\t\t\t\t\u003e;\n\t\t};\n\t};\n};\n....\n\n= linux-5.10 opensbi-0.9 DTS Example\n\nThe XuanTie C9xx DTB provided to OpenSBI generic firmware will usually have\n\"riscv,clint0\", \"riscv,plic0\", compatible strings.\n\n....\n/dts-v1/;\n/ {\n\tmodel = \"Test Sample\";\n\tcompatible = \"test,sample\";\n\t#address-cells = \u003c2\u003e;\n\t#size-cells = \u003c2\u003e;\n\n\tmemory@60000000 {\n\t\tdevice_type = \"memory\";\n                Caution: Determine your own address here\n\t\treg = \u003c0x0 0x60000000 0x0 0x40000000\u003e;\n\t};\n\n\tcpus {\n\t\t#address-cells = \u003c1\u003e;\n\t\t#size-cells = \u003c0\u003e;\n\t\ttimebase-frequency = \u003c25000000\u003e;\n\t\tcpu@0 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = \u003c0\u003e;\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"riscv\";\n\t\t\triscv,isa = \"rv64ima\";\n\t\t\tmmu-type = \"riscv,sv39\";\n\t\t\tcpu0_intc: interrupt-controller {\n\t\t\t\t#address-cells = \u003c0\u003e;\n\t\t\t\t#interrupt-cells = \u003c1\u003e;\n\t\t\t\tcompatible = \"riscv,cpu-intc\";\n\t\t\t\tinterrupt-controller;\n\t\t\t};\n\t\t};\n\t\tcpu@1 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = \u003c1\u003e;\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"riscv\";\n\t\t\triscv,isa = \"rv64ima\";\n\t\t\tmmu-type = \"riscv,sv39\";\n\t\t\tcpu1_intc: interrupt-controller {\n\t\t\t\t#address-cells = \u003c0\u003e;\n\t\t\t\t#interrupt-cells = \u003c1\u003e;\n\t\t\t\tcompatible = \"riscv,cpu-intc\";\n\t\t\t\tinterrupt-controller;\n\t\t\t};\n\t\t};\n\t\tcpu@2 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = \u003c2\u003e;\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"riscv\";\n\t\t\triscv,isa = \"rv64ima\";\n\t\t\tmmu-type = \"riscv,sv39\";\n\t\t\tcpu2_intc: interrupt-controller {\n\t\t\t\t#address-cells = \u003c0\u003e;\n\t\t\t\t#interrupt-cells = \u003c1\u003e;\n\t\t\t\tcompatible = \"riscv,cpu-intc\";\n\t\t\t\tinterrupt-controller;\n\t\t\t};\n\t\t};\n\t\tcpu@3 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = \u003c3\u003e;\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"riscv\";\n\t\t\triscv,isa = \"rv64ima\";\n\t\t\tmmu-type = \"riscv,sv39\";\n\t\t\tcpu3_intc: interrupt-controller {\n\t\t\t\t#address-cells = \u003c0\u003e;\n\t\t\t\t#interrupt-cells = \u003c1\u003e;\n\t\t\t\tcompatible = \"riscv,cpu-intc\";\n\t\t\t\tinterrupt-controller;\n\t\t\t};\n\t\t};\n\t};\n\n\n\tsoc {\n\t\t#address-cells = \u003c2\u003e;\n\t\t#size-cells = \u003c2\u003e;\n\t\tcompatible = \"simple-bus\";\n\t\tranges;\n\n\t\tclint0: clint@c000000 {\n\t\t\tcompatible = \"riscv,clint0\";\n\t\t\tinterrupts-extended = \u003c\n\t\t\t\t\u0026cpu0_intc  3 \u0026cpu0_intc  7\n\t\t\t\t\u0026cpu1_intc  3 \u0026cpu1_intc  7\n\t\t\t\t\u0026cpu2_intc  3 \u0026cpu2_intc  7\n\t\t\t\t\u0026cpu3_intc  3 \u0026cpu3_intc  7\n\t\t\t\t\u003e;\n\t\t\treg = \u003c0x0 0x0c000000 0x0 0x04000000\u003e;\n                Caution: Determine your own address here\n\t\t\tclint,has-no-64bit-mmio;\n\t\t};\n\n\t\tintc: interrupt-controller@8000000 {\n\t\t\t#address-cells = \u003c0\u003e;\n\t\t\t#interrupt-cells = \u003c1\u003e;\n\t\t\tcompatible = \"riscv,plic0\";\n\t\t\treg = \u003c0x0 0x08000000 0x0 0x04000000\u003e;\n                Caution: Determine your own address here\n\t\t\triscv,ndev = \u003c64\u003e;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts-extended = \u003c\n\t\t\t\t\u0026cpu0_intc  0xffffffff \u0026cpu0_intc  9\n\t\t\t\t\u0026cpu1_intc  0xffffffff \u0026cpu1_intc  9\n\t\t\t\t\u0026cpu2_intc  0xffffffff \u0026cpu2_intc  9\n\t\t\t\t\u0026cpu3_intc  0xffffffff \u0026cpu3_intc  9\n\t\t\t\t\u003e;\n\t\t};\n\t};\n};\n....\n\n= CPU gdbinit script\n\n....\n# Set gdb environment\nset confirm off\nset height  0\nmonitor set resume-bkpt-exception on\n\n# memory layout\nset $opensbi_addr = 0x60000000\nset $vmlinux_addr = $opensbi_addr + 0x00400000\nset $rootfs_addr  = $opensbi_addr + 0x04000000\nset $dtb_addr     = $vmlinux_addr - 0x00100000\nset $zsb_addr     = $vmlinux_addr - 0x00008000\nset $flag_addr    = $vmlinux_addr - 0x100\n\n# Load kernel\nrestore zero_stage_boot.bin binary          $zsb_addr\nrestore \u003cpreceding dts example\u003e.dtb binary  $dtb_addr\nrestore fw_dynamic.bin binary               $opensbi_addr\nrestore Image binary                        $vmlinux_addr\n\n# Set boot flag for CPU functional setting\n# This flag.BIT[0] makes zsb enable RV64XT32 by setting mxstatus.[63]=1\n# set *(unsigned int *)$flag_addr = 0x1\n# This flag.BIT[1] makes zsb enable COPINSTEE by setting mxstatus.[24]=1 \u0026\u0026 mxstatus.[22]=0\n# set *(unsigned int *)$flag_addr = 0x2\n# This flag.BIT[2] makes zsb enable XTINSTEE by setting mxstatus.[22]=1\n# set *(unsigned int *)$flag_addr = 0x4\nset *(unsigned int *)$flag_addr = 0x0\n\n# Set fast memory base reg for c908x\n# set $mtnfastmba = 0xXXXX\n\n# PLIC delegate (Only opensbi-0.9 \u0026 Linux-5.10 need it)\nset *0x081ffffc=1\n\n# Set all harts reset address (reset controller demo according to your SoC definition)\nset *0x18030010 = $zsb_addr\nset *0x18030018 = $zsb_addr\nset *0x18030020 = $zsb_addr\nset *0x18030028 = $zsb_addr\nset *0x18030030 = $zsb_addr\nset $pc         = $zsb_addr\n\n# Release all harts from reset\nset *0x18030000 = 0x7f\n\n# If you don't have a reset controller in SoC, and harts reset into bootrom's loop code.\n# Then, Use below method:\n# thread 1\n# set $pc = $zsb_addr\n# thread 2\n# set $pc = $zsb_addr\n# thread 3\n# set $pc = $zsb_addr\n# thread 4\n# set $pc = $zsb_addr\n# thread 5\n# set $pc = $zsb_addr\n# -ex \"c\" would let all harts jump to $zsb_addr.\n....\n\n= Run\n\nStart Jtag Server.\n\n....\nDebugServerConsole -prereset\n....\n\nThen use gdb connect the Jtag Server.\n\n....\nriscv64-elf-gdb -ex \"tar remote \u003cJtag Server ip:port\u003e\" -x \u003cyour soc gdbinit\u003e -x \u003cpreceding cpu gdbinit\u003e -ex \"c\"\n....\n\nUse `ctrl+c` to get into the gdb shell.\n\n....\nfile vmlinux\nsource gdbmarcos.txt\ndmesg\n....\n\ngdbmacros.txt:\n\nhttps://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/admin-guide/kdump/gdbmacros.txt\n\nvmlinux: The Linux kernel ELF file\n\n= Appendix A - PMU in DTS\n\nThe configuration of PMU can be referred to link:https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md[OpenSBI SBI PMU extension]\n\nThe following is an example of PMU configuration for the Xuantie C-series CPU written according to the datasheet.\n....\npmu {\n\tcompatible = \"riscv,pmu\";\n\triscv,event-to-mhpmevent =\n\t\t/* PMU_HW_BRANCH_INSTRUCTIONS -\u003e inst_branch */\n\t\t\u003c0x00005 0x00000000 0x00000036\u003e,\n\t\t/* PMU_HW_BRANCH_MISSES -\u003e inst_branch_mispredict */\n\t\t\u003c0x00006 0x00000000 0x00000038\u003e,\n\t\t/* PMU_HW_STALLED_CYCLES_FRONTEND -\u003e ifu_stalled_cycle */\n\t\t\u003c0x00008 0x00000000 0x00000027\u003e,\n\t\t/* PMU_HW_STALLED_CYCLES_BACKEND -\u003e idu_stalled_cycle */\n\t\t\u003c0x00009 0x00000000 0x00000028\u003e,\n\t\t/* L1D_READ_ACCESS -\u003e l1_dcache_read_access */\n\t\t\u003c0x10000 0x00000000 0x0000000c\u003e,\n\t\t/* L1D_READ_MISS -\u003e l1_dcache_read_miss */\n\t\t\u003c0x10001 0x00000000 0x0000000d\u003e,\n\t\t/* L1D_WRITE_ACCESS -\u003e l1_dcache_write_access */\n\t\t\u003c0x10002 0x00000000 0x0000000e\u003e,\n\t\t/* L1D_WRITE_MISS -\u003e l1_dcache_write_miss */\n\t\t\u003c0x10003 0x00000000 0x0000000f\u003e,\n\t\t/* L1I_READ_ACCESS -\u003e l1_icache_access */\n\t\t\u003c0x10008 0x00000000 0x00000001\u003e,\n\t\t/* L1I_READ_MISS -\u003e l1_icache_miss */\n\t\t\u003c0x10009 0x00000000 0x00000002\u003e,\n\t\t/* LL_READ_ACCESS -\u003e ll_cache_read_access */\n\t\t\u003c0x10010 0x00000000 0x00000010\u003e,\n\t\t/* LL_READ_MISS -\u003e ll_cache_read_miss */\n\t\t\u003c0x10011 0x00000000 0x00000011\u003e,\n\t\t/* LL_WRITE_ACCESS -\u003e ll_cache_write_access */\n\t\t\u003c0x10012 0x00000000 0x00000012\u003e,\n\t\t/* LL_WRITE_MISS -\u003e ll_cache_write_miss */\n\t\t\u003c0x10013 0x00000000 0x00000013\u003e,\n\t\t/* BPU_READ_ACCESS -\u003e branch_direction_prediction */\n\t\t\u003c0x10028 0x00000000 0x0000001c\u003e,\n\t\t/* BPU_READ_MISS -\u003e branch_direction_misprediction */\n\t\t\u003c0x10029 0x00000000 0x0000001b\u003e;\n\triscv,event-to-mhpmcounters =\n\t\t/* The Xuantie processor only implements 18 mhpmcounters, so the bitmap is 0x7fff8 */\n\t\t\u003c0x00005 0x00005 0x7fff8\u003e,\n\t\t\u003c0x00006 0x00006 0x7fff8\u003e,\n\t\t\u003c0x00008 0x00008 0x7fff8\u003e,\n\t\t\u003c0x00009 0x00009 0x7fff8\u003e,\n\t\t\u003c0x10000 0x10000 0x7fff8\u003e,\n\t\t\u003c0x10001 0x10001 0x7fff8\u003e,\n\t\t\u003c0x10002 0x10002 0x7fff8\u003e,\n\t\t\u003c0x10003 0x10003 0x7fff8\u003e,\n\t\t\u003c0x10008 0x10008 0x7fff8\u003e,\n\t\t\u003c0x10009 0x10009 0x7fff8\u003e,\n\t\t\u003c0x10010 0x10010 0x7fff8\u003e,\n\t\t\u003c0x10011 0x10011 0x7fff8\u003e,\n\t\t\u003c0x10012 0x10012 0x7fff8\u003e,\n\t\t\u003c0x10013 0x10013 0x7fff8\u003e,\n\t\t\u003c0x10028 0x10028 0x7fff8\u003e,\n\t\t\u003c0x10029 0x10029 0x7fff8\u003e;\n\triscv,raw-event-to-mhpmcounters =\n\t\t/* For raw event ID 0x0 - 0xff */\n\t\t\u003c0x0 0x0 0xffffffff 0xffffff00 0x7fff8\u003e;\n};\n....\n\nFor example, using `perf stat` \u0026 `perf record`:\n....\n# perf stat ls\n\n Performance counter stats for 'ls':\n\n             74.05 msec task-clock                       #    0.747 CPUs utilized\n                 0      context-switches                 #    0.000 /sec\n                 0      cpu-migrations                   #    0.000 /sec\n                58      page-faults                      #  783.256 /sec\n           3689065      cycles                           #    0.050 GHz\n           1336494      instructions                     #    0.36  insn per cycle\n            162119      branches                         #    2.189 M/sec\n             28716      branch-misses                    #   17.71% of all branches\n\n       0.099143960 seconds time elapsed\n\n       0.016153000 seconds user\n       0.092880000 seconds sys\n....\n\n....\n# echo 1000 \u003e /proc/sys/kernel/perf_event_max_sample_rate\n# perf record -g ls\nperf.data\n[ perf record: Woken up 1 times to write data ]\n[ perf record: Captured and wrote 0.006 MB perf.data (9 samples) ]\n....\n\n= Appendix B - How to compile perf\n\nWe can use buildroot to compile rootfs with perf tool.\n....\n# git clone https://github.com/buildroot/buildroot.git\n# cd buildroot/\n# make qemu_riscv64_virt_defconfig\n# make menuconfig\n....\n\nEnable the following PACKAGE config in menuconfig.\n....\nBR2_PACKAGE_LINUX_TOOLS=y\nBR2_PACKAGE_LINUX_TOOLS_PERF=y\nBR2_PACKAGE_ELFUTILS=y\n....\n\n= Appendix C - Additional DTS\n\nAdditional DTS examples(serial, bootargs with initrd):\n....\nserial@1900d000 {\n\tcompatible = \"snps,dw-apb-uart\";\n\treg = \u003c0x0 0x1900d000 0x0 0x400\u003e;\n\tinterrupt-parent = \u003c\u0026intc\u003e;\n\tinterrupts = \u003c20 4\u003e;\n\tclock-frequency = \u003c36000000\u003e;\n\tclock-names = \"baudclk\";\n\treg-shift = \u003c2\u003e;\n\treg-io-width = \u003c4\u003e;\n};\n\nchosen {\n\tbootargs = \"console=ttyS0,115200 norandmaps loglevel=7\";\n\tlinux,initrd-start = \u003c0x0 0x64000000\u003e;\n\tlinux,initrd-end = \u003c0x0 0x66000000\u003e;\n\tstdout-path = \"/soc/serial@1900d000:115200\";\n};\n....\n\nThe 'serial' needs to be configured based on the actual configuration of 'reg', 'interrupts', 'clock-frequency', while the 'chosen' needs to be configured based on the actual configuration of 'linux,initrd-start', 'linux,initrd-end'.\n\n= Appendix D - xuantie-link setting\n....\nset $mapbaddr2 [monitor i r 0xfc3]\nset $l3prxcr = $mapbaddr2 + 0xc0\nset $l3smpr  = $mapbaddr2 + 0x810\n Enable Cluster 0\nset *($l3prxcr) = 0x01\nset *($l3smpr) = 0x1\n# Enable Cluster 1\nset *($l3prxcr) = 0x11\nset *($l3smpr) = 0x1\n# Enable Cluster 2\nset *($l3prxcr) = 0x21\nset *($l3smpr) = 0x1\n# Enable Cluster 3\nset *($l3prxcr) = 0x31\nset *($l3smpr) = 0x1\n# Enable Cluster 4\nset *($l3prxcr) = 0x41\nset *($l3smpr) = 0x1\n# Enable Cluster 5\nset *($l3prxcr) = 0x51\nset *($l3smpr) = 0x1\n# Enable Cluster 6\nset *($l3prxcr) = 0x61\nset *($l3smpr) = 0x1\n# Enable Cluster 7\nset *($l3prxcr) = 0x71\nset *($l3smpr) = 0x1\nother operations\n# Disable proxy\nset *($l3prxcr) = 0x0\n\n# Close L3\n# set $l3decr = $stl3_base + 0x300\n# set *($l3decr) = 0x0\n....\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fxuantie-rv%2Fzero_stage_boot","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fxuantie-rv%2Fzero_stage_boot","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fxuantie-rv%2Fzero_stage_boot/lists"}