{"id":15394258,"url":"https://github.com/xyproto/literalcircuit","last_synced_at":"2026-07-02T16:33:35.416Z","repository":{"id":57520031,"uuid":"118438300","full_name":"xyproto/literalcircuit","owner":"xyproto","description":":arrow_forward: Programming language for implementing circuits in the style of \"literal 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The Literal Circuit Programming Language\n\nThis repository provides The Literal Circuit File Format Spec.\n\n## Literal Circuit File Format Spec\n\n* Spec version: 0.1\n* File extension: `.md`\n* The syntax is compatible with Markdown.\n\n## Defining a truth table\n\nThe name comes first, after `### `:\n\n    ### name\n\nThen comes the truth table, with one or more inputs, and arrow, and one or more outputs:\n\n    0 -\u003e 1\n    1 -\u003e 0\n\n### Example 1: xor\n\n    ### xor\n\n    0 0 -\u003e 0\n    0 1 -\u003e 1\n    1 0 -\u003e 1\n    1 1 -\u003e 0\n\n### Example 2: and\n\n    ### and\n\n    0 0 -\u003e 0\n    0 1 -\u003e 0\n    1 0 -\u003e 0\n    1 1 -\u003e 1\n\n### Example 3: or, with aliases A and B\n\n    ### or: A, B\n\n    0 0 -\u003e 0\n    0 1 -\u003e 1\n    1 0 -\u003e 1\n    1 1 -\u003e 1\n\n* Every line in a truth table must have an arrow (`-\u003e`), separating input and output.\n* If the name of a truth table has a colon (`:`), the rest of the line is expected to be a comma-separated list of aliases.\n\n## GateTables\n\nA circuit, with connections between gates, can be defined by a GateTable.\n\n* The arrow `-\u003e` is used to show what connects to what.\n* `i0` is the 0th input bit. `i1` is the 1st input bit. etc.\n* `o0` is the 0th output bit. `o1` is the 1st output bit. etc.\n* A colon (`:`)  can be used to separate multiple statements on one line.\n* A name or alias of a gate (as defined by a truth table) can be used in the circuit.\n* `.i0` and `.o0` can be used together with names or aliases of gates to select input and output bit positions.\n\n### Example 1: connecting inputs to \"A\" and then \"A\" to outputs\n\n    # OR Circuit 1\n\n    ### circuit\n\n    i0 -\u003e A.i0:A.o0 -\u003e o0\n    i1 -\u003e A.i1:A.o1 -\u003e o1\n\nThis connects input bit 0 to A (an alias for or, as defined above), then the output bit 0 from A to output bit 0 of the circuit.\nThe same is done for input bit 1, through A, and to output bit 1.\n\n## Special names\n\n* If a truth table is named \"test\", it will be used for testing the main circuit.\n* If a GateTable is named \"main\", then that is considered to be the main circuit.\n* If there is only one GateTable, then that is considered to be the main circuit.\n* `### ` is used to prefix names\n\n## Regular text\n\n* Text that does not begin with either `# `, `### `, or with four spaces and then contains an arrow (`-\u003e`), is ignored.\n* This means that it's completely acceptable (and encouraged) to include an ASCII-art diagram of the circuit in the circuit file. Example:\n\n```none\n    i0 ----\\\n            A------B-------- o0\n    i1 ----/      /\n                 /\n    i2 ----C----/\n          /\n    i3 --/\n```\n\nThe above diagram is indented with four spaces, but there are no arrows (`-\u003e`), which is why it works fine.\n\n* Explanations, comments, license and other information can also be included in the circuit.\n\n## Expansion\n\nA word that does not end with a number, between two arrows, in the definition of a GateTable, like this:\n\n`i0 -\u003e and -\u003e i1`\n\nWill be expanded like this:\n\n`i0 -\u003e and.i0:and.i1 -\u003e i1`\n\n# General information\n\n* Version: 0.1\n* License: MIT\n* Author: \u0026lt;xyproto@archlinux.org\u0026gt;\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fxyproto%2Fliteralcircuit","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fxyproto%2Fliteralcircuit","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fxyproto%2Fliteralcircuit/lists"}