{"id":31007645,"url":"https://github.com/yamil-serrano/risc-v-assembly-exercises","last_synced_at":"2025-09-13T03:11:57.887Z","repository":{"id":313961750,"uuid":"1053596296","full_name":"Yamil-Serrano/RISC-V-Assembly-Exercises","owner":"Yamil-Serrano","description":"A comprehensive collection of RISC-V Assembly exercises and practice programs for CIIC 4082: Computer Architecture II, designed to support learning and experimentation in low-level programming and computer architecture concepts.","archived":false,"fork":false,"pushed_at":"2025-09-09T17:23:44.000Z","size":4,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2025-09-09T20:56:22.472Z","etag":null,"topics":["32bit","assembly","ripes","risc-v"],"latest_commit_sha":null,"homepage":"","language":"Assembly","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Yamil-Serrano.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2025-09-09T17:00:24.000Z","updated_at":"2025-09-09T17:29:29.000Z","dependencies_parsed_at":"2025-09-09T20:56:23.754Z","dependency_job_id":"ab5381de-507b-4b8e-aa5f-7bd7399bf8c9","html_url":"https://github.com/Yamil-Serrano/RISC-V-Assembly-Exercises","commit_stats":null,"previous_names":["yamil-serrano/risc-v-assembly-exercises"],"tags_count":null,"template":false,"template_full_name":null,"purl":"pkg:github/Yamil-Serrano/RISC-V-Assembly-Exercises","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Yamil-Serrano%2FRISC-V-Assembly-Exercises","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Yamil-Serrano%2FRISC-V-Assembly-Exercises/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Yamil-Serrano%2FRISC-V-Assembly-Exercises/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Yamil-Serrano%2FRISC-V-Assembly-Exercises/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Yamil-Serrano","download_url":"https://codeload.github.com/Yamil-Serrano/RISC-V-Assembly-Exercises/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Yamil-Serrano%2FRISC-V-Assembly-Exercises/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":274911923,"owners_count":25372548,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-09-13T02:00:10.085Z","response_time":70,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["32bit","assembly","ripes","risc-v"],"created_at":"2025-09-13T03:11:54.976Z","updated_at":"2025-09-13T03:11:57.869Z","avatar_url":"https://github.com/Yamil-Serrano.png","language":"Assembly","funding_links":[],"categories":[],"sub_categories":[],"readme":"# RISC-V Assembly Exercises\n\nThis repository is a collection of **RISC-V Assembly practice programs** created as part of my coursework in **CIIC 4082: Computer Architecture II** at the University of Puerto Rico, Mayagüez. All examples were written and tested in the **[Ripes Simulator](https://github.com/mortbopet/Ripes)**, which provides an interactive environment to visualize registers, memory, and pipeline execution.\n\nThe programs included range from simple **array iterations** to basic algorithms, serving as a foundation for understanding how the RISC-V ISA works and reinforcing concepts learned in class.\n\n---\n\n## Why I Built This?\n\nIn **CIIC 4082**, we are introduced to **RISC-V programming**, which helps students understand the fundamentals of **low-level programming** and **computer architecture**.\n\nI created this repository to:\n\n* Practice **RISC-V Assembly instructions**, registers, and memory management.\n* Learn how to **iterate over arrays**, use **branches and loops**, and implement basic algorithms.\n* Build a personal reference of **RISC-V exercises** that can be reused or extended for more complex problems.\n\nThis collection documents my learning process and aims to help others who are starting with **RISC-V Assembly** as part of an academic course or self-study.\n\n---\n\n## How to Run (Ripes)\n\n1. Install [Ripes](https://github.com/mortbopet/Ripes).\n2. Clone this repository.\n3. Go to src folder and open any `.s` file in Ripes.\n4. Load the program and run it step by step or continuously.\n\n---\n\n## Technical Notes\n\n* All `.s` files are written in **RISC-V Assembly (32bits)**.\n* Memory is initialized in the `.data` section.\n* Code execution starts in the `.text` section.\n* Input/Output uses **ecall syscalls** supported by Ripes.\n\n---\n\n## License\n\nThis project is licensed under the MIT License – see the [LICENSE](LICENSE) file for details.\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyamil-serrano%2Frisc-v-assembly-exercises","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fyamil-serrano%2Frisc-v-assembly-exercises","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyamil-serrano%2Frisc-v-assembly-exercises/lists"}