{"id":24649221,"url":"https://github.com/yappy2000d/fpga-make-win","last_synced_at":"2025-03-20T18:48:23.957Z","repository":{"id":272827862,"uuid":"917570717","full_name":"yappy2000d/fpga-make-Win","owner":"yappy2000d","description":"Use the make tool to automate your work in CLI.","archived":false,"fork":false,"pushed_at":"2025-01-16T20:35:33.000Z","size":47,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-01-25T17:16:18.590Z","etag":null,"topics":["makefile","quartus","verilog"],"latest_commit_sha":null,"homepage":"","language":"Makefile","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"unlicense","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/yappy2000d.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2025-01-16T08:39:30.000Z","updated_at":"2025-01-16T20:35:34.000Z","dependencies_parsed_at":"2025-01-16T21:39:09.728Z","dependency_job_id":"e6e555d8-918d-462d-b020-4c786917fa76","html_url":"https://github.com/yappy2000d/fpga-make-Win","commit_stats":null,"previous_names":["yappy2000d/fpga-make-win"],"tags_count":0,"template":true,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yappy2000d%2Ffpga-make-Win","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yappy2000d%2Ffpga-make-Win/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yappy2000d%2Ffpga-make-Win/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yappy2000d%2Ffpga-make-Win/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/yappy2000d","download_url":"https://codeload.github.com/yappy2000d/fpga-make-Win/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":244675507,"owners_count":20491824,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["makefile","quartus","verilog"],"created_at":"2025-01-25T17:16:25.703Z","updated_at":"2025-03-20T18:48:23.931Z","avatar_url":"https://github.com/yappy2000d.png","language":"Makefile","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Building FPGAs with make tool\n\nUse the make tool to automate your work in CLI.\n\n**Compatible with Verilog (including SystemVerilog) and Windows only.**\n\n## Environments\n\n- GNU Make 4.4.1(Built for Windows32)\n- Intel Quartus II Web Edition(v13.0sp1 for Windows)\n- ModelSim-Intel(Starter Edition)\n\n## Usages\n\n1. Add `C:\\altera\\13.0sp1\\modelsim_ase\\win32aloem` and `C:\\altera\\13.0sp1\\modelsim_ase\\win32aloem` to PATH.\n2. Modify project name in [config file](/config#L2). (must be same as the Top-Level Entity)\n3. Before running the synthesis, change Devices in [syn/Makefile](/syn/Makefile#L41) file.\n4. Before running the post-simulation, update the variable named REGION in the [sim/Makefile](/sim/Makefile#L7) file.\n\n### Synthesis\n\nGenerate a .vo netlist and a standard delay format output (.sdo) file.\n\n\u003e [!IMPORTANT]  \n\u003e [Project name](/config#L2) must be same as the Top-Level Entity.\n\n\u003e [!TIP]\n\u003e Change Devices in [syn/Makefile](/syn/Makefile#L41) file.\n\n```ps1\nPS \\path\\to\\project\u003e cd syn; make all\n```\n\n### Pre-Sim\n\nRTL Functional Simulation.\n\n```ps1\nPS \\path\\to\\project\u003e cd sim; make pre-sim\n```\n\n### Post-Sim\n\nRun Gate-Level Simulation using .vo and .sdo files generated from synthesis.\n\n\u003e [!IMPORTANT]  \n\u003e Must run synthesis first. [REGION](/sim/Makefile#L7) must be same as the instance name in testbench.\n\n```ps1\nPS \\path\\to\\project\u003e cd sim; make post-sim\n```\n\n### Full workflow\n\npre-sim -\u003e synthesis -\u003e post-sim\n\n```ps1\nPS \\path\\to\\project\u003e make all\n```\n\n## Directory Structure\n\nAn example. Read more at https://blog.yappy2000.com/technology/fpga-make-win/\n\n    MyProject\n    │  config\n    │  Makefile\n    │  README\n    ├─sim\n    │      booth_tb.v\n    │      Makefile\n    ├─src\n    │      booth.v\n    └─syn\n           Makefile\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyappy2000d%2Ffpga-make-win","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fyappy2000d%2Ffpga-make-win","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyappy2000d%2Ffpga-make-win/lists"}