{"id":20962387,"url":"https://github.com/yasnakateb/pipelinedmips","last_synced_at":"2026-02-14T21:32:24.192Z","repository":{"id":131233396,"uuid":"291307695","full_name":"yasnakateb/PipelinedMIPS","owner":"yasnakateb","description":"🔮 A 16-bit MIPS Processor Implementation in Verilog HDL","archived":false,"fork":false,"pushed_at":"2020-08-30T07:58:01.000Z","size":77,"stargazers_count":11,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-10-11T02:09:13.881Z","etag":null,"topics":["cpu","icarus-verilog","iverilog","mips","mips-pipeline","mips-processor","pipeline","verilog","verilog-hdl"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/yasnakateb.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-08-29T16:30:28.000Z","updated_at":"2025-10-06T05:19:53.000Z","dependencies_parsed_at":null,"dependency_job_id":"d1c82b54-0c72-4167-b1cd-b400d9d28bf9","html_url":"https://github.com/yasnakateb/PipelinedMIPS","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/yasnakateb/PipelinedMIPS","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FPipelinedMIPS","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FPipelinedMIPS/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FPipelinedMIPS/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FPipelinedMIPS/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/yasnakateb","download_url":"https://codeload.github.com/yasnakateb/PipelinedMIPS/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FPipelinedMIPS/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29456247,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-14T21:29:27.764Z","status":"ssl_error","status_checked_at":"2026-02-14T21:28:11.111Z","response_time":53,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpu","icarus-verilog","iverilog","mips","mips-pipeline","mips-processor","pipeline","verilog","verilog-hdl"],"created_at":"2024-11-19T02:33:00.411Z","updated_at":"2026-02-14T21:32:24.175Z","avatar_url":"https://github.com/yasnakateb.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# PipelinedMIPS\nIn this project, a 16-bit pipelined MIPS processor is implemented in Verilog HDL.\n## Implementation\n### Stages\n\nMIPS pipeline has  five stages, with one step per stage:\n\n• IF: Instruction fetch from memory.\n\n• ID: Instruction decode \u0026 register read.\n\n• EX: Execute operation or calculate address.\n\n• MEM: Access memory operand.\n\n• WB: Write result back to register.\n\nEach stage takes in data from that buffer, processes it and write into the next buffer. Also note that as an instruction moves down the pipeline from one buffer to the next, its relevant information also moves along with it.\n\n### Instructions\n\n1. Add : R[rd] = R[rs] + R[rt]\n2. Subtract : R[rd] = R[rs] - R[rt]\n3. And: R[rd] = R[rs] \u0026 R[rt]\n4. Or : R[rd] = R[rs] | R[rt]\n5. SLT: R[rd] = 1 if R[rs] \u003c R[rt] else 0\n6. SLTI: R[rt] = 1 if R[rs] \u003c SignExtImm else 0\n7. Lw: R[rt] = M[R[rs]+SignExtImm]\n8. Sw : M[R[rs]+SignExtImm] = R[rt]\n9. Beq : if(R[rs]==R[rt]) PC=PC+1+BranchAddr\n10. J : PC=JumpAddr\n\n\n## observations\n\n\n* With pipelining, multiple instructions are overlapped during execution.\n* Latency is the same, but throughput  improves.\n* Pipeline rate limited by slowest pipeline stage.\n* Potential speedup = Number of pipe stages.\n\n\n## Dependencies\n### macOS\nThis project needs [Icarus-Verilog](http://iverilog.icarus.com) and a VCD viewer.\n\n\n\n## Building on macOS\n1. Icarus-Verilog can be installed via Homebrew :\n   \u003ccode\u003e$ brew install icarus-verilog\u003c/code\u003e\n2. Download [Scansion](http://www.logicpoet.com/scansion/) from here.  \n3. Clone the repository.\n4. Run \u003ccode\u003e$ make \u003c/code\u003e and type MIPS code to see it in binary form in rams_init_file.hex file. \n\n5. \u003ccode\u003e$ make simulate\u003c/code\u003e will: \n* compile design+TB\n* simulate the verilog design\n\n6. \u003ccode\u003e$ make display\u003c/code\u003e will: \n*  display waveforms.\n---\n 📌📌📌  You should use a for loop to dump array words in your test bench.\nCheck out these articles! \n1. [Verilog Portability Notes](https://iverilog.fandom.com/wiki/Verilog_Portability_Notes)\n2. [Icarus verilog dump memory array](https://stackoverflow.com/questions/20317820/icarus-verilog-dump-memory-array-dumpvars)\n\n### Data Path\n![](assets/datapath.png)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyasnakateb%2Fpipelinedmips","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fyasnakateb%2Fpipelinedmips","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyasnakateb%2Fpipelinedmips/lists"}