{"id":20962378,"url":"https://github.com/yasnakateb/threshold","last_synced_at":"2026-04-02T10:40:34.140Z","repository":{"id":131233425,"uuid":"242210010","full_name":"yasnakateb/Threshold","owner":"yasnakateb","description":"🖼✏️ Verilog-based Image Segmentation","archived":false,"fork":false,"pushed_at":"2025-05-13T16:09:26.000Z","size":1943,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2026-01-01T07:52:39.920Z","etag":null,"topics":["grayscale","image-processing","threshold","verilog","verilog-hdl","xilinx-ise"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/yasnakateb.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-02-21T18:57:43.000Z","updated_at":"2025-05-21T20:50:33.000Z","dependencies_parsed_at":null,"dependency_job_id":"63f4b527-28e4-4309-a3d0-058bba5e3d5e","html_url":"https://github.com/yasnakateb/Threshold","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/yasnakateb/Threshold","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FThreshold","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FThreshold/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FThreshold/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FThreshold/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/yasnakateb","download_url":"https://codeload.github.com/yasnakateb/Threshold/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FThreshold/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":31013958,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-27T02:58:54.984Z","status":"ssl_error","status_checked_at":"2026-03-27T02:58:46.993Z","response_time":164,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["grayscale","image-processing","threshold","verilog","verilog-hdl","xilinx-ise"],"created_at":"2024-11-19T02:32:54.173Z","updated_at":"2026-03-27T03:08:43.973Z","avatar_url":"https://github.com/yasnakateb.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# 🏁 Image Segmentation System\n\nImage  segmentation  is  a  fundamental  process  in  many  image,  video,  and  computer  vision applications. It is often used to partition an image into separate regions. Threshold  technique  is  one  of  the  important  techniques  in  image  segmentation. We can divide the pixels in the image into two major groups, according to their gray-level. In this project, threshold operation is implemented in Verilog. \n## Threshold Operation\n   The simplest approach to segment an image is using thresholding. The simplest thresholding methods replace each pixel in an image with a black pixel if the image intensity I (i,j)  is less than some fixed constant T, or a white pixel if the image intensity is greater than that constant.\n  \n## Implementation\nFirst argument is the source image, which should be a grayscale image. Second argument is the threshold value which is used to classify the pixel values. If pixel value is greater than a threshold value, it is assigned one value (white), else it is assigned another value (black).\n\n📌 Note: Verilog cannot read bitmap format file. So we will convert the image in \nbitmap format into hexadecimal file.\n* 📍 read_data:\n\tIn this module, there will be two parts. The first part is reading and the other\npart is processing. \n We use 3 intermediate signals RGB to save image data\nand a  Finite state machine for reading RGB888 data from memory and creating horizontal synchronization and vertical synchronization pulses.\n* 📍 write_data: In this module we will write the image (the processed image) into\na bitmap image.\n\n📌 Note: If you you change the image size, you'll have to change the bmp header. [More info](http://www.fastgraph.com/help/bmp_header_format.html).\n\n### Grayscale\nGrayscaling is the process of converting an image from other color spaces to shades of gray. It varies between complete black and complete white. An RGB image can be viewed as three images( a red scale image, a green scale image and a blue scale image). Each pixel has three different\ncomponents which are red, green and blue. Average method is the most simple one to convert an color image into a grayscale image. You just have to take the average of three colors. Since its an RGB image, so it means that you have add r with g with b and then divide it by 3 to get your desired grayscale image.\n\n![](ScreenShots/rgb.png)\n\n## Dependencies\n\nThis project needs [Xlinx ISE](https://en.wikipedia.org/wiki/Xilinx_ISE).\n\n### Building on Windows 10\n\n 1. Download Xilinx ISE from [here](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive-ise.html).\n\n  2. Clone the repository. \n  3. Simulate the design in hdl folder. (You you need to run 6ms in simulation).\n  4. Now you see that the output image will be available.\n\n### TODO\n - ⭕ Add threshold filter\n \n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyasnakateb%2Fthreshold","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fyasnakateb%2Fthreshold","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyasnakateb%2Fthreshold/lists"}