{"id":20962379,"url":"https://github.com/yasnakateb/uartcommunication","last_synced_at":"2026-03-19T18:14:03.358Z","repository":{"id":131233419,"uuid":"465662486","full_name":"yasnakateb/UARTCommunication","owner":"yasnakateb","description":"☎️ UART Communication Implementation in Verilog HDL","archived":false,"fork":false,"pushed_at":"2022-03-22T16:35:32.000Z","size":5,"stargazers_count":4,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-07-03T17:53:26.231Z","etag":null,"topics":["icarus-verilog","iverilog","serial-communication","uart","uart-interface","uart-protocol","uart-verilog","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/yasnakateb.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-03-03T09:59:41.000Z","updated_at":"2025-03-10T11:52:21.000Z","dependencies_parsed_at":null,"dependency_job_id":"29f289f5-1927-475e-9cc8-a0b5ff09a714","html_url":"https://github.com/yasnakateb/UARTCommunication","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/yasnakateb/UARTCommunication","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FUARTCommunication","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FUARTCommunication/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FUARTCommunication/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FUARTCommunication/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/yasnakateb","download_url":"https://codeload.github.com/yasnakateb/UARTCommunication/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yasnakateb%2FUARTCommunication/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29046503,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-03T10:09:22.136Z","status":"ssl_error","status_checked_at":"2026-02-03T10:09:16.814Z","response_time":96,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["icarus-verilog","iverilog","serial-communication","uart","uart-interface","uart-protocol","uart-verilog","verilog"],"created_at":"2024-11-19T02:32:54.522Z","updated_at":"2026-02-03T13:03:14.705Z","avatar_url":"https://github.com/yasnakateb.png","language":"Verilog","readme":"#  UART Communication\n\nUART is a universal serial communication protocol that transmits data serially between systems. It is an interface that sends out usually a byte at a time.\nThis interface is a simple way to connect an FPGA to a PC. We just need a transmitter and receiver module. The transmitter is essentially a special\nshift register that loads data in parallel and then shifts it out bit by bit at a specific rate. The receiver, on the other hand, shifts in data bit by bit and then reassembles the data. \n\n   \n\n## Building on macOS\n1. Icarus-Verilog can be installed via Homebrew :\n   \u003ccode\u003e$ brew install icarus-verilog\u003c/code\u003e\n2. Download [Scansion](http://www.logicpoet.com/scansion/) from here.  \n3. Clone the repository.\n4. Run \u003ccode\u003e$ make \u003c/code\u003e and type MIPS code to see it in binary form in rams_init_file.hex file. \n\n5. \u003ccode\u003e$ make simulate\u003c/code\u003e will: \n* compile design+TB\n* simulate the verilog design\n\n6. \u003ccode\u003e$ make display\u003c/code\u003e will: \n*  display waveforms.\n\n\n## Links\n1. [Design and Verification of UART using System Verilog](https://www.ijeat.org/wp-content/uploads/papers/v9i5/E1135069520.pdf)\n2. [FPGA Prototyping by Verilog Examples (UART)](https://academic.csuohio.edu/chu_p/rtl/fpga_vlog_book/fpga_vlog_sample_chapter.pdf)\n\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyasnakateb%2Fuartcommunication","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fyasnakateb%2Fuartcommunication","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyasnakateb%2Fuartcommunication/lists"}