{"id":51307547,"url":"https://github.com/yijunyu/tile-rs","last_synced_at":"2026-07-16T15:41:27.301Z","repository":{"id":366461705,"uuid":"1164536251","full_name":"yijunyu/tile-rs","owner":"yijunyu","description":"Safe Rust bindings for Huawei Ascend NPU (CANN framework)","archived":false,"fork":false,"pushed_at":"2026-07-15T07:48:52.000Z","size":1032,"stargazers_count":3,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2026-07-15T08:21:59.288Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Rust","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/yijunyu.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE-APACHE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2026-02-23T07:39:36.000Z","updated_at":"2026-07-15T07:49:02.000Z","dependencies_parsed_at":null,"dependency_job_id":null,"html_url":"https://github.com/yijunyu/tile-rs","commit_stats":null,"previous_names":["yijunyu/tile-rs"],"tags_count":1,"template":false,"template_full_name":null,"purl":"pkg:github/yijunyu/tile-rs","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yijunyu%2Ftile-rs","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yijunyu%2Ftile-rs/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yijunyu%2Ftile-rs/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yijunyu%2Ftile-rs/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/yijunyu","download_url":"https://codeload.github.com/yijunyu/tile-rs/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yijunyu%2Ftile-rs/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":35549640,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-05-26T15:22:16.424Z","status":"online","status_checked_at":"2026-07-16T02:00:06.687Z","response_time":83,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2026-07-01T01:00:33.712Z","updated_at":"2026-07-16T15:41:27.297Z","avatar_url":"https://github.com/yijunyu.png","language":"Rust","funding_links":[],"categories":["GPU Computing"],"sub_categories":[],"readme":"# tile-rs\n\n**tile-rs** is a Rust compiler framework for writing accelerator kernels *once* and lowering them to many hardware backends. You write kernels in a safe, idiomatic Rust tile DSL; a custom `rustc` codegen backend lowers them through MLIR to whichever target you select — the same source producing numerically-equivalent results across very different accelerators.\n\nThe same kernel lowers to **15 backends** through a pluggable registry — NVIDIA/AMD GPUs, Apple GPUs (Metal), Vulkan/SPIR-V, AWS Trainium, Huawei Ascend, and more. **Eight are validated end-to-end on real hardware today** — Apple Metal, Vulkan (MoltenVK), Huawei Ascend NPU, NVIDIA GPU, Google TPU, AWS Trainium, Intel Gaudi, and the portable `linalg`→CPU bridge (five with published [pu-rs.org](https://pu-rs.org) benchmark entries); the rest are codegen-proven and scaffolded for on-hardware bring-up.\n\n## Features\n\n- **Write once, target many** — a single Rust tile DSL (`tile_std`) lowers to 15 codegen backends through MLIR\n- **Pluggable backends** — a `CodegenTarget` registry picks the target at build time via `TILERS_CODEGEN_PATH`; adding a backend never touches kernel source\n- **Memory-safe kernels** — typed, RAII-style APIs structurally prevent whole classes of bugs common in hand-written accelerator C/C++\n- **Numerical equivalence** — generated kernels match a CPU reference *on real hardware* (validated on 8 targets: Apple Metal, Vulkan/MoltenVK, Huawei Ascend NPU, NVIDIA GPU, Google TPU, AWS Trainium, Intel Gaudi, and the `linalg`→CPU bridge — five with benchmark entries at [pu-rs.org](https://pu-rs.org); every backend is also checked by a codegen generality test suite)\n- **Prebuilt codegen backend** — the LLVM-linked backend ships as a release artifact; a kernel crate points `rustc` at it via `TILERS_CODEGEN_SO` + a bundled `.cargo/config.toml`, with no local LLVM build\n\n## Supported Targets\n\nThe same `tile_std` kernel lowers to each backend below, selected with `TILERS_CODEGEN_PATH`. Every backend is proven by a **codegen generality matrix** — each `convert_mlir_to_\u003cbackend\u003e` turns one shared MLIR module into syntactically-marked target source (15/15 tested). **On-HW** marks backends whose generated kernels are additionally validated end-to-end against a CPU reference on real hardware — via the [pu-rs.org](https://pu-rs.org) leaderboard (Metal, Ascend, NVIDIA, TPU, Trainium) and/or standalone runs (Vulkan on MoltenVK; Gaudi on a cloud instance; the `linalg` bridge on CPU).\n\n\u003c!-- BACKEND REPO LINKS (pre-staged): the per-backend repos are deployed PRIVATE.\n     Open-sourcing is ASYNCHRONOUS — when a backend repo is flipped public, link its\n     Backend cell below (linked-cell text is prepared in the private, non-deployed\n     BACKENDS_PRESTAGE.md). NEVER link a still-private repo. Currently public: Apple GPU (tile-rs-metal). --\u003e\n| Backend | `TILERS_CODEGEN_PATH` | Target language | Codegen | On-HW |\n|---------|----------------------|-----------------|:------:|-------|\n| [Apple GPU](https://github.com/yijunyu/tile-rs-metal) | `metal`   | Metal Shading Language       | ✅ | ✅ M2 Max / M4 |\n| Vulkan          | `vulkan`  | GLSL → SPIR-V                | ✅ | ✅ Apple Silicon (MoltenVK) |\n| Ascend NPU      | `cpp`, `pto` | AscendC C++ / PTO-MLIR    | ✅ | ✅ 910B |\n| NVIDIA GPU      | `cuda`    | CUDA C                       | ✅ | ✅ T4 / H20 |\n| Google TPU      | `tpu`     | JAX / Pallas                 | ✅ | ✅ v5e |\n| AWS Trainium    | `nki`     | NKI (Python)                 | ✅ | ✅ trn1 |\n| Intel Gaudi     | `gaudi`   | TPC-C                        | ✅ | ✅ Gaudi (cloud) |\n| Portable bridge | `linalg`  | MLIR `linalg` dialect        | ✅ | ✅ CPU |\n| Moore Threads   | `musa`    | MUSA                         | ✅ | — |\n| AMD Ryzen AI    | `aie`     | IRON (Python)                | ✅ | — |\n| Cambricon MLU   | `bang`    | BANG-C                       | ✅ | — |\n| Qualcomm Hexagon| `hexagon` | HVX / QNN                    | ✅ | — |\n| Cerebras        | `csl`     | CSL                          | ✅ | — |\n| Tenstorrent     | `ttmetal` | Tensix                       | ✅ | — |\n\nAll 15 emit their target language (codegen-tested); **8 are validated end-to-end on real hardware** today — Apple Metal (M2 Max / M4), Vulkan/SPIR-V (MoltenVK on Apple Silicon), Huawei Ascend NPU (910B), NVIDIA GPU (Tesla T4 / H20, via `mlir_to_cuda`), Google TPU (v5e, via `mlir_to_tpu` Pallas), AWS Trainium (trn1, via `mlir_to_nki`), Intel Gaudi (cloud, via `mlir_to_gaudi`), and the portable `linalg` bridge (CPU). Five carry published [pu-rs.org](https://pu-rs.org) benchmark entries (Metal, Ascend, NVIDIA, TPU, Trainium); Vulkan, Gaudi, and the CPU `linalg` path are validated by standalone runs.\n\n## Architecture\n\ntile-rs is backend-agnostic at its core. A Rust kernel is lowered to MLIR *once*, then a pluggable backend converts that MLIR to the selected target's source — so the same kernel runs on very different hardware:\n\n```\n                Rust kernel  (tile_std DSL)\n                       │\n                       ▼\n              rustc_codegen_tile        custom rustc backend: MIR → MLIR\n                       │\n                       ▼\n                     MLIR ──►  CodegenTarget registry\n                                    │\n        ┌──────────┬──────────┬─────┴────┬──────────┬───────────────┐\n        ▼          ▼          ▼          ▼          ▼               ▼\n     Metal       CUDA C     SPIR-V     AscendC     NKI       AIE / TPC / …\n   Apple GPU    NVIDIA      Vulkan     Ascend    Trainium   Ryzen AI / Gaudi\n```\n\nEach backend supplies its own host runtime, registered behind the `CodegenTarget` trait.\n\n### Crates (target-agnostic framework)\n\n| Crate | Purpose |\n|-------|---------|\n| `tile_std` | Kernel-side DSL: tile intrinsics + buffer API, `#![no_core]` device runtime |\n| `tile_std_macros` | Kernel attribute macros |\n| `tile_codegen` | The `CodegenTarget` trait + `TargetRegistry` — the pluggable backend skeleton |\n| `tile_spec` | Executable Gherkin (Given/When/Then) spec layer + the codegen-generality test suite |\n| `tile_hal` | Vendor-neutral Hardware Abstraction Layer (host-side device/stream/buffer + backend selection) |\n| `rustc_codegen_tile` | Custom rustc codegen backend (MIR → MLIR → backend source). The 15 backend **emitters** are open source — `src/mlir_to_*.rs`, exercised by `tile_spec`. The LLVM-dependent backend that links them into a runnable `librustc_codegen_tile.so` is distributed as a prebuilt release artifact (it needs LLVM 20; the emitters do not). |\n\n## Quick Start\n\n```bash\ncurl -fsSL https://raw.githubusercontent.com/yijunyu/tile-rs/main/scripts/install.sh | bash\n```\n\n## License\n\nLicensed under either of [MIT](LICENSE-MIT) or [Apache-2.0](LICENSE-APACHE) at\nyour option.\n\nUnless you explicitly state otherwise, any contribution intentionally submitted\nfor inclusion in the work by you, as defined in the Apache-2.0 license, shall be\ndual licensed as above, without any additional terms or conditions.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyijunyu%2Ftile-rs","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fyijunyu%2Ftile-rs","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyijunyu%2Ftile-rs/lists"}