{"id":18627535,"url":"https://github.com/yugr/gatecheck","last_synced_at":"2025-07-06T15:08:11.772Z","repository":{"id":129418839,"uuid":"167780828","full_name":"yugr/gatecheck","owner":"yugr","description":"Yet another Verilog static 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is a sloppy script which looks for violations\nof gating requirements (all registers wider than 4 bits\nmust be clock-gated).\n\nScript is intentinally simple, ignoring macro and treating\nglobal, cross-module analysis in fast but primitive way.\n\nFor info on usage, run\n```\n$ gatecheck.pl --help\n```\n\nTODO (must):\n* merge splitted definition of module inputs/outputs e.g.\n```\nmodule mod(input x);\nreg [2:0] x;\n```\n\nTODO (may):\n* parse concatenations in NBAs i.e. `{x,y} \u003c= ...`\n* respect parameter assignments in module instantiations\n* delay warning till parameter is actually used to calculate some register width\n* evaluate more types of expressions (indexing, `clog2()`, etc.)\n\nKnown issues:\n* global parameter matching algorithm is extremely naive\n  so may easily match wrong parameters (seems to be precise enough\n  for current sources though)\n* declaration of same register under different\n  branches of macro or parameter condition will\n  result in \"duplicate declaration\" warnings:\n```\n`ifdef AMBER_WISHBONE_DEBUG\n reg  [7:0]              jitter_r = 8'h0f;\n reg  [1:0]              start_read_r = 'd0;\n`else\n reg                     start_read_r = 'd0;\n`endif\n```\n* declaration of same register in tasks will result\n  in \"duplicate declarations\" warnings\n* macro in the middle of construct will break parsing:\n```\nmodule test(\n  output ddr3_ck_n,\n`ifdef XILINX_SPARTAN6_FPGA\n  inout mcb3_rzq,\n`endif\n);\n```\n* macro definition of range will cause parse errors:\n```\nwire [`MY_SIZE] x;\n```\n* Verilog attributes are not parsed:\n```\n(* keep = \"true\", max_fanout = 30 *) output  reg   [DATA_WIDTH-1:0]   data;\n```\n* delays are not parsed:\n```\nr \u003c= #25 0;\nwire #1 cpci_rd_wr_L;\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyugr%2Fgatecheck","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fyugr%2Fgatecheck","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyugr%2Fgatecheck/lists"}