{"id":46407947,"url":"https://github.com/yuravg/uvm_tb_cross_bar","last_synced_at":"2026-03-05T12:35:51.634Z","repository":{"id":55431276,"uuid":"215959746","full_name":"yuravg/uvm_tb_cross_bar","owner":"yuravg","description":"SystemVerilog UVM testbench example","archived":false,"fork":false,"pushed_at":"2024-05-08T07:47:47.000Z","size":228,"stargazers_count":20,"open_issues_count":0,"forks_count":10,"subscribers_count":4,"default_branch":"master","last_synced_at":"2024-05-08T08:43:06.097Z","etag":null,"topics":["systemverilog","uvm","verification"],"latest_commit_sha":null,"homepage":null,"language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/yuravg.png","metadata":{"files":{"readme":"README.org","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2019-10-18T06:53:34.000Z","updated_at":"2024-05-08T07:47:34.000Z","dependencies_parsed_at":"2023-01-22T17:15:14.679Z","dependency_job_id":null,"html_url":"https://github.com/yuravg/uvm_tb_cross_bar","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/yuravg/uvm_tb_cross_bar","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yuravg%2Fuvm_tb_cross_bar","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yuravg%2Fuvm_tb_cross_bar/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yuravg%2Fuvm_tb_cross_bar/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yuravg%2Fuvm_tb_cross_bar/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/yuravg","download_url":"https://codeload.github.com/yuravg/uvm_tb_cross_bar/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yuravg%2Fuvm_tb_cross_bar/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30124655,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-05T11:11:57.947Z","status":"ssl_error","status_checked_at":"2026-03-05T11:11:29.001Z","response_time":93,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["systemverilog","uvm","verification"],"created_at":"2026-03-05T12:35:51.490Z","updated_at":"2026-03-05T12:35:51.607Z","avatar_url":"https://github.com/yuravg.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"#+title: SystemVerilog UVM testbench example\n#+author: Yuriy Gritsenko\n#+startup: inlineimages\n\n=uvm_tb_cross_bar= is my a SystemVerilog UVM example.\nIt has DUT, testbench and scripts to run simulation.\n\n* DUT\nA =cross_bar= project is used as DUT, this is just a bus switcher([[./rtl/doc/README.md][specification]]).\nUsed my implementation of this design.\n\n=DUT= implementation is located in the =rtl= directory.\n\n** RTL synthesis\n\nFor RTL synthesis is used Intel Quartus Prime, example is located in the =quartus= directory.\n\n#+begin_src text\n|-rtl/\n#+end_src\n\n* Testbench\nThe testbench has /bus/ and /cross-bar/ UVC.\n\n/Bus/ UVC has /agent/ and /sequences/.\n\n/Cross-bar/ UVC has /agent/, connecting /layer/ and /sequences/.\nThe /layer/ provides connectivity /cross-bar/ and /bus/ UVC.\n\n/Env/ has /scoreboard/ and connect /cross-bar/ agents.\nThe /scoreboard/ is checking results of each /tests/.\n\n/TB/ provides connection /RLT/ to UVM /Test/.\n\nEach /Test/ connects /Env/ to /DUT/ and runs required /virtual_sequences/.\nThe result of all sequences is checked using /scoreboard/.\n\n#+begin_src text\n|-agents/\n| |_bus_uvc/\n| |_cross_bar_uvc/\n-uvm_tb/\n  |_env/\n  |_tb/\n  |_tests/\n  |_virtual_sequences/\n#+end_src\n* Simulation\nTo run simulation of this example used Mentor Graphic's QuestaSim or ModelSim simulator.\n\nDirectory =sim= contains files to run simulation.\n\nFollowing examples of commands to be run from the =sim= directory.\n\n#+begin_src text\n|-sim/\n#+end_src\n\n** Simulation launch\nTo run the simulation used console and make-file.\n\nTo get list of available commands or =list of tests= should run following command from console:\n\n#+BEGIN_SRC shell-script\n$ make help\n#+END_SRC\n\n** Run complete verification\nRun command from console:\n\n#+BEGIN_SRC shell-script\n$ make all_tests\n#+END_SRC\n\nThe results of each test and a summary of all the tests are displayed in the console.\n\nEach test writes a log and report files: \u003ctest_name\u003e.log, \u003ctest_name\u003e.log.rpt\n(report file - it is just reformatted the log file).\n\n*** Log-file output example\n\n[[./images/end_of_test_log.png]]\n\n*** Rpt-file output example\n\n[[./images/end_of_test_rpt.png]]\n\n*** Summary example\n\n[[./images/summary.png]]\n\n** Run some test\nAt this example there are following ways to run tests:\n1. run test in console(without GUI)\n2. run test with GUI from console\n3. run test from GUI\n\n*** 1. Run test in console(without GUI)\nTo run test just run command from console:\n\n#+BEGIN_SRC shell-script\n$ make \u003ctest_name\u003e\n#+END_SRC\n\n\u003ctest_name\u003e - name from =list of tests=\n\n*** 2. run test with GUI from console\nShould set empty environment variable /VSIM_MODE/, and run test in console (example for BASH):\n\n#+BEGIN_SRC shell-script\n$ export VSIM_MODE=''\n$ make \u003ctest_name\u003e\n#+END_SRC\nor\n#+BEGIN_SRC shell-script\n$ make \u003ctest_name\u003e VSIM_MODE=''\n#+END_SRC\n\n\u003ctest_name\u003e - name from =list of tests=\n\n*** 3. run test from GUI\nRun ModelSim/QuestaSim, load aliases, run test.\n\n- Run ModelSim/QuestaSim in =sim= directory\n#+BEGIN_SRC shell-script\n$ vsim `pwd` \u0026\n#+END_SRC\n\n- run in ModelSim/QuestaSim _Transcript_ window\n#+BEGIN_SRC tcl\ndo alias.do\n#+END_SRC\n\n- run test\n#+BEGIN_SRC tcl\nrun_\u003ctest_name\u003e\n#+END_SRC\n\n* Screenshots\n\nMentor Graphic's QuestaSim wave\n\n[[./images/wave.png]]\n\n* License\n\nThis project is licensed under the MIT License. If not, see [[https://www.opensource.org/licenses/MIT]]\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyuravg%2Fuvm_tb_cross_bar","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fyuravg%2Fuvm_tb_cross_bar","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fyuravg%2Fuvm_tb_cross_bar/lists"}