{"id":21434364,"url":"https://github.com/z1skgr/vhdl-processor-charis","last_synced_at":"2026-02-05T05:01:52.827Z","repository":{"id":163130797,"uuid":"315145334","full_name":"z1skgr/VHDL-processor-CHARIS","owner":"z1skgr","description":"Architecture of processor designed in vhdl","archived":false,"fork":false,"pushed_at":"2024-12-05T11:44:03.000Z","size":17215,"stargazers_count":2,"open_issues_count":1,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-07-10T10:53:48.675Z","etag":null,"topics":["boolean-algebra","computer-architecture","computer-architectures","custom-commands","forwarding","hardware","hazards","isa","logic-programming","pipeline-processor","processor-architecture","vhdl"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/z1skgr.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-11-22T22:31:56.000Z","updated_at":"2024-12-19T09:16:02.000Z","dependencies_parsed_at":null,"dependency_job_id":"00b714b0-2143-4279-bf26-e1358ae240f1","html_url":"https://github.com/z1skgr/VHDL-processor-CHARIS","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/z1skgr/VHDL-processor-CHARIS","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/z1skgr%2FVHDL-processor-CHARIS","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/z1skgr%2FVHDL-processor-CHARIS/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/z1skgr%2FVHDL-processor-CHARIS/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/z1skgr%2FVHDL-processor-CHARIS/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/z1skgr","download_url":"https://codeload.github.com/z1skgr/VHDL-processor-CHARIS/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/z1skgr%2FVHDL-processor-CHARIS/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29113188,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-05T03:44:17.043Z","status":"ssl_error","status_checked_at":"2026-02-05T03:44:12.077Z","response_time":65,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["boolean-algebra","computer-architecture","computer-architectures","custom-commands","forwarding","hardware","hazards","isa","logic-programming","pipeline-processor","processor-architecture","vhdl"],"created_at":"2024-11-22T23:34:57.753Z","updated_at":"2026-02-05T05:01:52.800Z","avatar_url":"https://github.com/z1skgr.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Memory\n\u003e Building components to develop processor in VHDL\n\n ## Table of contents\n* [Labs](#labs)\n   * [1](#alu-and-register-file)\n   * [2](#datapath-charis-processor)\n   * [3](#control-unit)\n   * [4](#operations-for-calculator-design)\n   * [5](#pipeline-proc) \n* [How to run](#how-to-run)\n* [Acknowledgments](#acknowledgments)\n\n\n### ALU and REGISTER FILE\n#### ALU\n\n| Name |  Width  |  Action  | \n| ------- | ---------- | ---------| \n| Α | IN (32 bits) | 2's compiment operative| \n| Β | IN (32 bits) |  2's compiment operative | \n| Op | IN (4 bits) | Action code | \n| Out | OUT (32 bits)|  2's compiment result | \n| Zero | IN (1 bit) | Signal for Zero output|  \n| C\u003csub\u003eout\u003c/sub\u003e | OUT (1 bit) | Signal for Carry Out output | \n| Ovf | OUT (1 bit) | Signal for Overflow output | \n\n\u003cbr\u003e\n\n| Code |  Action  |  Result  | \n| ------- | ---------- | ---------- | \n| 0000 | Add | Out = A + B| \n| 0001 | Sub |  Out = A - B | \n| 0010 | Logic NOT AND |Out = A NAND B | \n| 0011 | Logic OR|  Out = A OR B | \n| 0100 | Reverse Input | Out = !A|  \n| 1000 | Arithmetic shift right | Out = (int)A\u003e\u003e1 | \n| 1001 | Logic shift right | Out = (unsigned int)A\u003e\u003e1| \n| 1010 | Logic shift left | Out = A\u003c\u003c1 | \n| 1100 | Rotate shift left | Rotate from MSB to LSB | \n| 1101 | Rotate shift right | Rotate from LSB to MSB | \n \n \u003cbr\u003e\n \n #### REG\n| Name |  Width  |  Action  | \n| -------- | ---------- | ---------- | \n| Αrd1 | IN (5 bits) | Address source register #1| \n| Ard2 | IN (5 bits) |  Address source register #2| \n| Awr | IN (5 bits) | Address destination register | \n| Dout1 | OUT (32 bits)|  Data  register #1 | \n| Dout2 | OUT (32 bit) | Data  register #2|  \n| Din | IN (32 bits) | Data for writing | \n| WrEn | IN (1 bit) | Enable writing | \n| Clk | IN (1 bit) | Clock | \n\n\u003cbr\u003e\n\n### Datapath CHARIS processor\n#### R type\n| Name |  Width  | \n| --------- | ------- | \n| Opcode | 6 bits | \n| rs | 5 bits |  \n| rd | 5 bits|\n| rt | 5 bits|  \n| not-used | 5 bits | \n| func | 6 bits | \n\n\u003cbr\u003e\n\n#### I type\n| Name |  Width  | \n| --------- | ------- | \n| Opcode | 6 bits | \n| rs | 5 bits |  \n| rd | 5 bits|\n| Immediate | 16 bits|  \n\n\u003cbr\u003e\n\n| Opcode |  Func  |  Comm  |  Action\n| --------- | -------- | -------- | ----------- | \n| 100000 | 110000 | add | RF[rd]\u003c-RF[rs]+RF[rt] | \n| 100000 | 110001 |  sub | RF[rd]\u003c-RF[rs]-RF[rt]| \n| 100000 | 110010 | nand | RF[rd]\u003c-RF[rs] NAND RF[rt] | \n| 100000 | 110100| not | RF[rd]\u003c-!RF[rs] | \n| 100000 | 110011 | or |  RF[rd]\u003c-RF[rs] OR RF[rt] | \n| 100000| 111000 | sra | RF[rd]\u003c-RF[rs]\u003e\u003e1| \n| 100000| 111001 | sll | RF[rd]\u003c-RF[rs]\u003c\u003c1 (logical) | \n| 100000 | 111010  | srl | RF[rd]\u003c-RF[rs]\u003e\u003e1 (logical) | \n| 100000| 111100 | rol | RF[rd]\u003c-Rotate left(RF[rs]) | \n| 100000| 111101 | ror | RF[rd]\u003c-Rotate right(RF[rs]) | \n| 111000| - | li | RF[rd]\u003c-SignExtend(Imm) | \n| 111001| - | lui | RF[rd]\u003c-Imm\u003c\u003c 16 (zero fill) | \n| 110000| - | addi | RF[rd]\u003c-RF[rs] + SignExtend(Imm) | \n| 110010| - | nandi | RF[rd]\u003c-RF[rs] NAND ZeroFill(Imm) | \n| 110011| - | ori | RF[rd]\u003c-RF[rs] | ZeroFill(Imm) | \n| 111111| - | b | PC\u003c-PC + 4 + (SignExtend(Imm)\u003c\u003c2 |\n| 000000| - | beq | Branch when equal sources | \n| 000001| - | bne | Branch when not equal sources| \n| 000011| - | lb | RF[rd]\u003c- ZeroFill(31 downto 8) \u0026 MEM[RF[rs]+SignExtend(Imm)](7 downto 0) | \n| 000111| - | sb | MEM[RF[rs]+SignExtend(Imm)]\u003c-ZeroFill(31 down to 8) \u0026 RF[rd][7 downto 0] | \n| 001111| - | lw | RF[rd]\u003c- MEM[RF[rs]+SignExtend(Imm)] | \n| 011111| - | sw | MEM[RF[rs]+SignExtend(Imm)]\u003c-RF[rd] | \n\n\u003cbr\u003e\n\n#### Features\n* MAIN MEMORY 2048x32\n* IF STAGE\n* DECODE\n* ALU\n* MEM\n\n\u003cbr\u003e\n \n### Control Unit\n* Connection of the stages.\n* Design FSM for control signals.\n\n\u003cbr\u003e\n\n### Advanced Custom commands\n1. addi_MMX_byte\n  * ![1](https://user-images.githubusercontent.com/22920222/160410956-6742740c-d041-4e64-b46b-62da78837427.png)\n2. poly2 \n  * ![2](https://user-images.githubusercontent.com/22920222/160410960-521744a1-e1fa-4702-8cff-fb3a31071ffa.png)\n4. rfld\n   * Loads RF registers from 31 consecutive memory locations\n5. rfst\n   * Stores the values of the RF registers in 31 consecutive memory locations\n\n\u003cbr\u003e\n\n| Opcode |  Func  |  Comm  |  Action\n| ------- | ------- | -------- | ------------------------------------------------------ | \n| 110001 | - | MMX_addi_byte | RF[rd]\u003c-RF[rs](31 downto 24) + immed(7 downto 0) \u0026..\u0026 RF[rd]\u003c-RF[rs](7 downto 0) + immed(7 downto 0) | \n| 100000 | 010000 |  poly2 | RF[rd]\u003c- RF[rt]* RF[rt] * MEM[RF[rs]] + RF[rt]* MEM[RF[rs]+4]+ MEM[RF[rs]+8]| \n| 011100 | - | rfld | base_addr = RF[rs]+ SignExtend(Imm) for(i=1;i\u003c32;i++) RF[i]\u003c-MEM[base_addr+4*i]  | \n| 011110 | - | rfst | base_addr = RF[rs]+ SignExtend(Imm) for(i=1;i\u003c32;i++) MEM[base_addr+4*i]\u003c-RF[i] | \n\n\u003cbr\u003e\n\n### Pipeline proc\n1. Mods on Datapath\n   * new registers\n   * solve stalls/forwarding\n3. Modification on Control\n   * solve hazards (data/control)\n\n\n## How to run\nXilinx ISE® design suite 13.7 and above\n\nTo run the project \n\n1. Install Xilinx suite from https://www.xilinx.com/downloadNav/vivado-design-tools/archive-ise.html\n2. Clone code from [git](https://github.com/z1skgr/Tomasulo-BASED-processor)\n3. File \u003e Import \u003e Existing Projects into Workspace \u003e Locate project \n   * Copy projects into workspace if you do want to copy the project files to your current workspace location.\n\nTo run the simulation (.wcfg) \n1. Find simulation files in hierarchy\n   * Import them if they do not appear\n2. Simulate behavioral model\n3. Check system behavior based on scenarios (different input signal)\n\nProjects were created in older version of Xilinx. \u003cbr\u003e\nFor incompatibility issues, make an new project and copy `.vhd` files.\n\n\n## Acknowledgements\n* This project was created for the requirements of the lesson Computer Οrganization\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fz1skgr%2Fvhdl-processor-charis","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fz1skgr%2Fvhdl-processor-charis","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fz1skgr%2Fvhdl-processor-charis/lists"}