{"id":13416907,"url":"https://github.com/zachjs/sv2v","last_synced_at":"2025-05-16T15:09:00.057Z","repository":{"id":41037607,"uuid":"169686321","full_name":"zachjs/sv2v","owner":"zachjs","description":"SystemVerilog to Verilog conversion","archived":false,"fork":false,"pushed_at":"2025-04-06T18:29:07.000Z","size":2299,"stargazers_count":616,"open_issues_count":31,"forks_count":58,"subscribers_count":16,"default_branch":"master","last_synced_at":"2025-04-22T20:49:07.595Z","etag":null,"topics":["conversion","systemverilog","verilog","yosys"],"latest_commit_sha":null,"homepage":"","language":"Haskell","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/zachjs.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2019-02-08T04:49:52.000Z","updated_at":"2025-04-22T12:59:00.000Z","dependencies_parsed_at":"2023-12-26T21:21:33.551Z","dependency_job_id":"d6fa9cae-4a58-4e40-b90b-760873182ac9","html_url":"https://github.com/zachjs/sv2v","commit_stats":{"total_commits":929,"total_committers":10,"mean_commits":92.9,"dds":"0.011840688912809427","last_synced_commit":"eca8714de776b963f2edfbd9b51557966885f9ca"},"previous_names":[],"tags_count":12,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zachjs%2Fsv2v","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zachjs%2Fsv2v/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zachjs%2Fsv2v/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zachjs%2Fsv2v/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/zachjs","download_url":"https://codeload.github.com/zachjs/sv2v/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":254553958,"owners_count":22090417,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["conversion","systemverilog","verilog","yosys"],"created_at":"2024-07-30T22:00:29.361Z","updated_at":"2025-05-16T15:08:55.043Z","avatar_url":"https://github.com/zachjs.png","language":"Haskell","funding_links":[],"categories":["Meta HDL and Transpilers","Haskell","Circuit Compilers","Hardware Description Language","Frameworks"],"sub_categories":[],"readme":"# sv2v: SystemVerilog to Verilog\n\nsv2v converts SystemVerilog ([IEEE 1800-2017]) to Verilog ([IEEE 1364-2005]),\nwith an emphasis on supporting synthesizable language constructs.\n\n[IEEE 1800-2017]: https://ieeexplore.ieee.org/servlet/opac?punumber=8299593\n[IEEE 1364-2005]: https://ieeexplore.ieee.org/servlet/opac?punumber=10779\n\nThe primary goal of this project is to create a completely free and open-source\ntool for converting SystemVerilog to Verilog. While methods for performing this\nconversion already exist, they generally either rely on commercial tools, or are\nlimited in scope.\n\nThis project was originally developed to target [Yosys], and so allows for\ndisabling the conversion of (passing through) those [SystemVerilog features that\nYosys supports].\n\n[Yosys]: https://yosyshq.net/yosys/\n[SystemVerilog features that Yosys supports]: https://github.com/YosysHQ/yosys#supported-features-from-systemverilog\n\nThe idea for this project was shared with me while I was an undergraduate at\nCarnegie Mellon University as part of a joint Computer Science and Electrical\nand Computer Engineering research project on open hardware under Professors [Ken\nMai] and [Dave Eckhardt]. I have greatly enjoyed collaborating with the team at\nCMU since January 2019, even after my graduation the following May.\n\n[Ken Mai]: https://engineering.cmu.edu/directory/bios/mai-kenneth.html\n[Dave Eckhardt]: https://www.cs.cmu.edu/~davide/\n\n\n## Dependencies\n\nAll of sv2v's dependencies are free and open-source.\n\n* Build Dependencies\n    * [Haskell Stack](https://www.haskellstack.org/) - Haskell build system\n    * Haskell dependencies are managed in `sv2v.cabal`\n* Test Dependencies\n    * [Icarus Verilog](https://steveicarus.github.io/iverilog/) - for Verilog\n      simulation\n    * [shUnit2](https://github.com/kward/shunit2) - test framework\n    * Python 3.x - for evaluating certain test cases\n\n\n## Installation\n\n### Pre-built binaries\n\nBinaries for Ubuntu, macOS, and Windows are available on the [releases page]. If\nyour system is not covered, or you would like to build the latest commit, simple\ninstructions for building from source are below.\n\n[releases page]: https://github.com/zachjs/sv2v/releases\n\n### Building from source\n\nYou must have [Stack] installed to build sv2v. Then you can:\n\n[Stack]: https://www.haskellstack.org/\n\n```\ngit clone https://github.com/zachjs/sv2v.git\ncd sv2v\nmake\n```\n\nThis creates the executable at `./bin/sv2v`. Stack takes care of installing\nexact (compatible) versions of the compiler and sv2v's build dependencies.\n\nYou can install the binary to your local bin path (typically `~/.local/bin`) by\nrunning `stack install`, or copy over the executable manually.\n\n\n## Usage\n\nsv2v takes in a list of files and prints the converted Verilog to `stdout` by\ndefault. Users should typically pass all of their SystemVerilog source files to\nsv2v at once so it can properly resolve packages, interfaces, type parameters,\netc., across files. Using `--write=adjacent` will create a converted `.v` for\nevery `.sv` input file rather than printing to `stdout`. `--write`/`-w` can also\nbe used to specify a path to a `.v` output file. Undefined modules and\ninterfaces can be automatically loaded from library directories using\n`--libdir`/`-y`.\n\nUsers may specify `include` search paths, define macros during preprocessing,\nand exclude some of the conversions. Specifying `-` as an input file will read\nfrom `stdin`.\n\nBelow is the current usage printout.\n\n```\nsv2v [OPTIONS] [FILES]\n\nPreprocessing:\n  -I --incdir=DIR           Add a directory to the include search path\n  -y --libdir=DIR           Add a directory to the library search path used\n                            when looking for undefined modules and interfaces\n  -D --define=NAME[=VALUE]  Define a macro for preprocessing\n     --siloed               Lex input files separately, so macros from\n                            earlier files are not defined in later files\n     --skip-preprocessor    Disable preprocessing of macros, comments, etc.\nConversion:\n     --pass-through         Dump input without converting\n  -E --exclude=CONV         Exclude a particular conversion (Always, Assert,\n                            Interface, Logic, SeverityTask, or UnbasedUnsized)\n  -v --verbose              Retain certain conversion artifacts\n  -w --write=MODE/FILE/DIR  How to write output; default is 'stdout'; use\n                            'adjacent' to create a .v file next to each input;\n                            use a path ending in .v to write to a file; use a\n                            path to an existing directory to create a .v within\n                            for each converted module\n     --top=NAME             Remove uninstantiated modules except the given\n                            top module; can be used multiple times\nOther:\n     --oversized-numbers    Disable standard-imposed 32-bit limit on unsized\n                            number literals (e.g., 'h1_ffff_ffff, 4294967296)\n     --dump-prefix=PATH     Create intermediate output files with the given\n                            path prefix; used for internal debugging\n     --bugpoint=SUBSTR      Reduce the input by pruning modules, wires, etc.,\n                            that aren't needed to produce the given output or\n                            error substring when converted\n     --help                 Display this help message\n     --version              Print version information\n     --numeric-version      Print just the version number\n```\n\n\n## Supported Features\n\nsv2v supports most synthesizable SystemVerilog features. Current notable\nexceptions include `defparam` on interface instances, certain synthesizable\nusages of parameterized classes, and the `bind` keyword. Assertions are also\nsupported, but are simply dropped during conversion.\n\nIf you find a bug or have a feature request, please [create an issue].\nPreference will be given to issues that include examples or test cases.\n\n[create an issue]: https://github.com/zachjs/sv2v/issues/new\n\n\n## SystemVerilog Front End\n\nThis project contains a preprocessor, lexer, and parser, and an abstract syntax\ntree representation for a subset of the SystemVerilog specification. The parser\nis not very strict. The AST allows for the representation of syntactically (and\nsemantically) invalid Verilog. The goal is to be more general in the\nrepresentation to enable more standardized and straightforward conversion\nprocedures. This could be extended into an independent and more fully-featured\nfront end if there is significant interest.\n\n\n## Testing\n\nOnce the [test dependencies] are installed, tests can be run with `make test`.\nGitHub Actions is used to [automatically test] commits. Please review the [test\ndocumentation] for guidance on adding, debugging, and interpreting tests.\n\n[test dependencies]: #dependencies\n[test documentation]: test/README.md\n[automatically test]: https://github.com/zachjs/sv2v/actions\n\nThere is also a [SystemVerilog compliance suite] that tests open-source tools'\nSystemVerilog support. Although not every test in the suite is applicable, it\nhas been a valuable asset in finding edge cases.\n\n[SystemVerilog compliance suite]: https://github.com/chipsalliance/sv-tests\n\n\n## Acknowledgements\n\nThis project was originally forked from [Tom Hawkin's Verilog parser]. While the\nfront end has changed substantially to support the larger SystemVerilog\nstandard, his project was a great starting point.\n\n[Tom Hawkin's Verilog parser]: https://github.com/tomahawkins/verilog\n\nReid Long was invaluable in developing this tool, providing significant tests\nand advice, and isolating many bugs.\n\nEdric Kusuma helped me with the ins and outs of SystemVerilog, with which I had\nno prior experience, and has also helped with test cases.\n\nSince sv2v's public release, many people have taken the time to file detailed\nbug reports and feature requests. I greatly appreciate their help in furthering\nthe project.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fzachjs%2Fsv2v","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fzachjs%2Fsv2v","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fzachjs%2Fsv2v/lists"}