{"id":20530084,"url":"https://github.com/zackteo/16-bit-alu-mojo","last_synced_at":"2026-03-11T00:02:26.495Z","repository":{"id":81540967,"uuid":"218698324","full_name":"zackteo/16-bit-ALU-mojo","owner":"zackteo","description":"16 bit ALU using MOJO FPGA ","archived":false,"fork":false,"pushed_at":"2019-11-06T04:20:59.000Z","size":3738,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-03-06T02:23:17.357Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/zackteo.png","metadata":{"files":{"readme":"README.org","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-10-31T06:23:34.000Z","updated_at":"2019-11-06T04:21:01.000Z","dependencies_parsed_at":"2023-09-06T14:46:45.274Z","dependency_job_id":null,"html_url":"https://github.com/zackteo/16-bit-ALU-mojo","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/zackteo/16-bit-ALU-mojo","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zackteo%2F16-bit-ALU-mojo","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zackteo%2F16-bit-ALU-mojo/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zackteo%2F16-bit-ALU-mojo/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zackteo%2F16-bit-ALU-mojo/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/zackteo","download_url":"https://codeload.github.com/zackteo/16-bit-ALU-mojo/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zackteo%2F16-bit-ALU-mojo/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30362705,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-10T21:41:54.280Z","status":"ssl_error","status_checked_at":"2026-03-10T21:40:59.357Z","response_time":106,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-15T23:35:21.925Z","updated_at":"2026-03-11T00:02:26.467Z","avatar_url":"https://github.com/zackteo.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"#+STARTUP: showall\n\n* 16-bit Arithmetic Logic Unit (ALU) \n2-input 16-bit ALU using the Lucid programming language for the Mojo V3 FPGA (Field-programmable gate array) development board (Spartan 6).\n** Done by:\n   - Zachary Teo\n   - Amanda Kosim\n   - Wong Wei En Matthew\n   - Chow Jia Yi\n** Functionality\n*** Standard ALU operations \n**** Arithmetic (+, -)\n     - Zero, Z\n       - indicating all bits of S are logic zero\n     - Negative, N\n       - indicating the result is a negative\n     - Overflow, V\n       - indicating the result has exceeded the numeric range of S\n**** Bitwise logical (AND, NAND, OR, NOR, XOR, \"A\", \"B\") \n**** Bit Shift (SL, SR, SLA, SRA) \n**** Comparison (==, \u003c, \u003c=)\n**** Multiply (/*)\n*** Additional Functionality\n    - Automated testing\n      - The program uses a Finite State Machine (FSM) to iterate throught a series of test cases for the various operations our ALU is capable of performing. Flow is shown below\n[[./Flow.png]]\n*** Table of functions\n| ALUFN [5:4] | ALUFN[3:0] | Short-form | Operation                        |\n|-------------+------------+------------+----------------------------------|\n|          00 |       0000 | ADD        | Addition (+)                     |\n|             |       0001 | SUB        | Subtraction (-)                  |\n|             |       0010 | MUL        | Multiply (*)                     |\n|-------------+------------+------------+----------------------------------|\n|          01 |       1000 | AND        | A \u0026 B                            |\n|             |       0111 | NAND       | ~(A \u0026 B)                         |\n|             |       1110 | OR         | A or B                           |\n|             |       0001 | NOR        | ~(A or B)                        |\n|             |       0110 | XOR        | A ^ B                            |\n|             |       1010 | \"A\"        | (A)                              |\n|             |       0101 | \"B\"        | (B)                              |\n|-------------+------------+------------+----------------------------------|\n|          10 |       0000 | SHL        | Shift Left (\u003e\u003e)                  |\n|             |       0001 | SHR        | Shift Right (\u003c\u003c)                 |\n|             |       0011 | SHRA       | Shift Right Arithmetically (\u003c\u003c\u003c) |\n|-------------+------------+------------+----------------------------------|\n|          11 |       0011 | COMPEQ     | Equal (==)                       |\n|             |       0101 | COMPLT     | Less than (\u003c)                    |\n|             |       0111 | COMPLE     | Less than or Equal (\u003c=)          |\n** Implementation\nThe 16-bit is made of the modules below and implemented as its own ALU module, making it hierarchical and modular, for reusability.\nThe ALU module is then implemented in mojo_top.luc\n- Adder module\n  - part 1: adding/subtracting input A to/by input B\n  - part 2: taking S to evaluate z,v,n\n- Boolean module\n  - bitwise AND, NAND, OR, NOR, XOR, \"A\", \"B\" for inputs A and B\n- Compare module\n  - uses z,v,n from part 2 of adder to evaluate ==,\u003c,\u003c=\n- Shifter module\n  - shift input A by input B (bits) for SHL, SHR, SHRA\n- Multiply module\n  - get the lower 16 bits when input A is multiplied by input B\n  \n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fzackteo%2F16-bit-alu-mojo","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fzackteo%2F16-bit-alu-mojo","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fzackteo%2F16-bit-alu-mojo/lists"}