{"id":18564526,"url":"https://github.com/zannatul-naim/digital-system-design","last_synced_at":"2026-03-19T05:05:18.781Z","repository":{"id":50968367,"uuid":"520173235","full_name":"Zannatul-Naim/Digital-System-Design","owner":"Zannatul-Naim","description":"Digital System Design Lab Codes using Verilog","archived":false,"fork":false,"pushed_at":"2022-11-27T09:04:25.000Z","size":54,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-05-15T18:47:23.659Z","etag":null,"topics":["adder","d-flipflop","flipflop","full-adder","half-adder","jk-flipflop","ripple-carry-adder","t-flipflop","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Zannatul-Naim.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2022-08-01T15:54:21.000Z","updated_at":"2025-03-25T14:32:35.000Z","dependencies_parsed_at":"2023-01-23T13:45:16.423Z","dependency_job_id":null,"html_url":"https://github.com/Zannatul-Naim/Digital-System-Design","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/Zannatul-Naim/Digital-System-Design","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Zannatul-Naim%2FDigital-System-Design","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Zannatul-Naim%2FDigital-System-Design/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Zannatul-Naim%2FDigital-System-Design/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Zannatul-Naim%2FDigital-System-Design/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Zannatul-Naim","download_url":"https://codeload.github.com/Zannatul-Naim/Digital-System-Design/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Zannatul-Naim%2FDigital-System-Design/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":269302528,"owners_count":24394493,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-08-07T02:00:09.698Z","response_time":73,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["adder","d-flipflop","flipflop","full-adder","half-adder","jk-flipflop","ripple-carry-adder","t-flipflop","verilog"],"created_at":"2024-11-06T22:15:34.405Z","updated_at":"2026-02-08T20:12:28.944Z","avatar_url":"https://github.com/Zannatul-Naim.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Digital-System-Design\nDigital System Design Lab verilog codes\n\n\n### Basic Gates\n\n  - [OR GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/or_gate.v)\n  - [AND GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/and_gate.v)\n  - [NOT GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/not_gate.v)\n  - [NAND GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/nand_gate.v)\n  - [NOR GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/nor_gate.v)\n  - [X-OR GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/xor_gate.v)\n  - [X-NOR GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/xnor_gate.v)\n\n\n### Code Converter\n\n  - [Binary to Gray conversion](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Code-Converter/binary_to_gray.v)\n  - [Gray to Binary conversion](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Code-Converter/gray_to_binary.v)\n  - [BCD to Excess-3](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Code-Converter/bcd_to_excess3.v)\n  - [Excess-3 to BCD](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Code-Converter/excess3_to_bcd.v)\n\n\n### Adder\n  - [Half Adder](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Adder/half_adder.v)\n  - [Full Adder (using half adder)](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Adder/full_adder.v)\n  - [Full Adder (without using half adder)](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Adder/fullAdder.v)\n  - [4 Bit Ripple Carry Adder](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Adder/4_bit_ripple_carry_adder.v)\n  - [4 Bit Carry Lookahead Adder](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Adder/carry_look_ahead_adder.v)\n\n### Subtractor\n  - [Half Subtractor](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Subtractor/half_subtractor.v)\n  - [Full Subtractor](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Subtractor/full_subtractor.v)\n\n### Adder-Subtractor\n  - [4 bit adder subtractor](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Adder-Subtractor/adder_subtractor_4_bit.v)\n  \n### Comparator\n  - [2 bit comparator](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Comparator/2_bit_comparator.v)\n\n### Multiplexer\n  - [2x1 MUX](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Multiplexer/2x1_multiplexer.v)\n  - [Enable 2x1 MUX](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Multiplexer/enable_2x1_multiplexer.v)\n  - [4x1 MUX](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Multiplexer/4x1_multiplexer.v)\n  - [4x1 MUX using 2x1 MUX](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Multiplexer/4x1_mux_using_2x1.v)\n  - [8x1 MUX](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Multiplexer/8x1_mux.v)\n\n\n### Multiplier\n  - [2x2 Array Multiplier](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Multiplier/2x2_multiplier.v) \n\n\n### Flip Flops\n\n  - [JK FlipFlop](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/FlipFlops/jk_flipflop.v)\n  - [D FlipFlop](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/FlipFlops/d_flipflop.v)\n  - [D flipflop using SR flipflop with clear input](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/FlipFlops/d_flipflop_with_clear.v)\n  - [T FlipFlop](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/FlipFlops/t_flipflop.v)\n  - [Master Slave JK flipflop](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/FlipFlops/master_slave_jk_flipflp.v)\n\n\n### Counters\n  - \u003cb\u003eSynchronous\u003c/b\u003e\n    - [4 bit random sequence](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Counter/Synchronous/random_sequence_sync_counter_4_bit.v)\n    - [3 Bit Synchronous Up/Down](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Counter/Synchronous/3_bit_Synchronous_up-down_counter.v)\n    \n  - \u003cb\u003eAsynchronous\u003c/b\u003e\n    - [4 bit ripple counter or mod-16 counter](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Counter/Asynchronous/4_bit_ripple_counter.v)\n    - [Mod - 10 Counter](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Counter/Asynchronous/mod_10_async.v)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fzannatul-naim%2Fdigital-system-design","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fzannatul-naim%2Fdigital-system-design","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fzannatul-naim%2Fdigital-system-design/lists"}