{"id":21899597,"url":"https://github.com/zephray/risu064","last_synced_at":"2026-02-20T22:39:32.375Z","repository":{"id":44696759,"uuid":"507139099","full_name":"zephray/RISu064","owner":"zephray","description":"Dual-issue RV64IM processor for fun \u0026 learning","archived":false,"fork":false,"pushed_at":"2023-07-04T19:17:16.000Z","size":4969,"stargazers_count":64,"open_issues_count":1,"forks_count":9,"subscribers_count":4,"default_branch":"master","last_synced_at":"2026-01-14T16:01:32.084Z","etag":null,"topics":["risc-v"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/zephray.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-06-24T20:41:43.000Z","updated_at":"2025-08-13T09:26:53.000Z","dependencies_parsed_at":"2024-11-28T14:45:29.273Z","dependency_job_id":"06383d2c-2a54-4af3-8f4e-d278c5b48b78","html_url":"https://github.com/zephray/RISu064","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/zephray/RISu064","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zephray%2FRISu064","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zephray%2FRISu064/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zephray%2FRISu064/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zephray%2FRISu064/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/zephray","download_url":"https://codeload.github.com/zephray/RISu064/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zephray%2FRISu064/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29667093,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-20T19:49:36.704Z","status":"ssl_error","status_checked_at":"2026-02-20T19:44:05.372Z","response_time":59,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["risc-v"],"created_at":"2024-11-28T14:45:21.953Z","updated_at":"2026-02-20T22:39:32.349Z","avatar_url":"https://github.com/zephray.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# RISu064\n\n\u003cimg src=\"doc/vol6.jpg\" alt=\"illustration\" width=\"400\"/\u003e\n\nRISu64 (Reduced Instruction Set μProcessor 64 / Squirrel 64) is a series of my toy 64-bit RISC-V compatible processors. RISu064 (this repo) is the first in the series. Illustration by [Andy Lithia](https://github.com/andylithia).\n\n## Features\n\n![pipeline_diagram](doc/pipeline.svg)\n\n- RV64IMZicsr_Zifencei instruction set\n- 7-stage pipeline: PCGen(F1), IMem(F2), Decode(ID), Issue(IX), Execute(EX), DMem(MEM), Writeback(WB).\n- In-order issue and out-of-order writeback\n- Dual-issue\n- BTB + Bimodal/Gselect/Gshare/Tournament + RAS branch predictors\n- 2x Integer (arithmetic, barrel shifter, branch)\n- 1x Load store unit (aligned access only, unaligned access generate precise exception)\n- 1x Multiply/ divide unit (non-pipelined, 3/6-cycle 32/64bit multiply, 34/66-cycle 64bit divide)\n- Multiply/ divide is optional\n- Optional L1 instruction and data cache (2-way set associative blocking cache)\n- Machine mode with exception and interrupt support\n- Optional experimental hardware refilled MMU + supervisor and user mode support\n- Written in portable synthesizable Verilog\n\n## Performance\n\nThe performance varies based on configurations:\n\n- Single-issue + 512-entry Bimodal + 32-entry BTB + TCM: 3.01 Coremark/MHz\n- Single-issue + 4K-entry Tournament + 32-entry BTB + TCM: 3.06 Coremark/MHz\n- Single-issue + 4K-entry Tournament + 32-entry BTB + 16KB L1$: 3.01 Coremark/MHz\n- Dual-issue + 4K-entry Tournament + 32-entry BTB + TCM: 4.31 Coremark/MHz\n\nNote:\n\n1. Compiled with GCC 9.2.0, with the following options: ```-MD -O3 -mabi=lp64 -march=rv64im -mcmodel=medany -ffreestanding -nostdlib -fomit-frame-pointer -funroll-all-loops -finline-limit=1000 -ftree-dominator-opts -fno-if-conversion2 -fselective-scheduling -fno-code-hoisting -freorder-blocks-and-partition```\n2. Single-issue is no longer supported in the latest branch, testing was carried out using commit ```efd0d3```\n3. L1-cache is organized as 2-way set associative, 16KB each, with simulated unlimited L2 memory and 15-cycle latency\n4. Each BPU entry is 2-bit, internally it expects 8-bit wide memory interface. 4K-entry = 1K x 8bit SRAM\n\n## Area\n\nThe area is quite big right now (rather poor PPA).\n\nFPGA:\n\nCurrently the multiplier is not optimized for FPGA yet. With Aritx-7 XC7A100T-3CSG324C:\n\n- Multiplier disabled, no cache: ~120 MHz fmax, 19.6K LUT, 6.9K FF\n\nThe critical path is at write-back stage.\n\nASIC:\n\nThe project has been submitted to Google + efabless MPW-7 shuttle for tapeout, with a 5GHz narrow-band RF transceiver.\n\n![asic](doc/MPW71.jpg)\n\nThe total area allocated to this project is about 8.5mm^2. The core is configured to be:\n\n- 4K depth Gshare predictor\n- 8KB 2-way I-cache + 8KB 2-way D-cache\n- Hardware multiplier and divider enabled\n- MMU disabled, machine mode only\n\nTotal area allocated to core minus SRAM cell is about 3.4mm^2, with around 39% utilization. Assuming 85% target placement density, this translate to a 1.56mm^2 die area at SKY130 process with SKY130HD cell library.\n\nRegarding maximum frequency, without SRAM/ cache, Fmax is around 100MHz with CLA+KSA hybrid adder, or 80MHz with inferred adder. With cache, tag comparsion logic becomes the critical path and Fmax drops to about 50MHz.\n\n## Status\n\nThis project is mostly a proof-of-concept and is regarded as done. There might be bug fixes in the future, but don't expect major changes.\n\n## Running Simulation\n\nIn sim folder, run make. It should build the simulator.\n\nTo run coremark, build the coremark by running ```make``` in tests/coremark, then in the sim folder do ```./simulator --ram ../tests/coremark/coremark.bin```.\n\nNote: Verilator required for building the simulator. RV64 gcc (riscv64-unknown-elf-gcc) required for building the coremark.\n\n## Debugging RTL\n\nThe core implementation probably contains bugs. Due to its OoO WB without reordering design, the core's architectural state would often diverge from ISA model, making lock-step co-simulation or trace comparsion with ISA simulation hard. A trace comparison tool is provided to allow comparing between RTL simulator generated trace and Spike generated trace. Example usage:\n\n```\nspike -m0x20000000:4096,0x80000000:1048576 -l --log-commits tests/coremark/coremark.elf 2\u003e spike.log\nsim/simulator --ram tests/coremark/coremark.bin --cycles 10000 \u003e sim.log\ntests/trace_comparater.py --risu sim.log --spike spike.log\n```\n\nDifferences (if any) will be reported.\n\n## Acknowledgements\n\nDuring the design of this processor, I have used the following projects as reference:\n\n- [lowRISC's muntjac](https://github.com/lowRISC/muntjac), Apache 2.0 license\n- [UltraEmbedded's biriscv](https://github.com/ultraembedded/biriscv), Apache 2.0 license\n\nThe following third-party code have been used:\n\n- [Gary Guo's round robin arbiter](https://garyguo.net/), BSD license\n\n## License\n\nMIT\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fzephray%2Frisu064","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fzephray%2Frisu064","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fzephray%2Frisu064/lists"}