{"id":13668054,"url":"https://github.com/zhanghai/archexp","last_synced_at":"2025-04-26T18:31:05.292Z","repository":{"id":70274235,"uuid":"54038225","full_name":"zhanghai/archexp","owner":"zhanghai","description":"浙江大学计算机体系结构课程实验","archived":true,"fork":false,"pushed_at":"2016-10-19T08:56:59.000Z","size":3156,"stargazers_count":167,"open_issues_count":0,"forks_count":28,"subscribers_count":2,"default_branch":"master","last_synced_at":"2024-11-11T03:35:37.550Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/zhanghai.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.md","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2016-03-16T14:21:00.000Z","updated_at":"2024-11-06T03:31:48.000Z","dependencies_parsed_at":"2023-02-24T21:00:29.065Z","dependency_job_id":null,"html_url":"https://github.com/zhanghai/archexp","commit_stats":null,"previous_names":[],"tags_count":4,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zhanghai%2Farchexp","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zhanghai%2Farchexp/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zhanghai%2Farchexp/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/zhanghai%2Farchexp/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/zhanghai","download_url":"https://codeload.github.com/zhanghai/archexp/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":251035341,"owners_count":21526350,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T07:01:02.608Z","updated_at":"2025-04-26T18:31:00.874Z","avatar_url":"https://github.com/zhanghai.png","language":"Verilog","funding_links":[],"categories":["Verilog"],"sub_categories":[],"readme":"# 浙江大学计算机体系结构课程实验\n\n张海\n\n本项目是我按照课程要求独立完成的 MIPS 流水线 CPU 实现。目前已实现 31 条指令和 Stall/Forwarding。\n\n本项目的开发使用 Nexys 3 开发板进行，但应当可以很简单地移植到其他开发板。\n\n本项目的二进制 .bit 文件可以在 [Releases](https://github.com/DreaminginCodeZH/archexp/releases/) 中下载。\n\n## 原因\n\n课程提供的代码在结构、命名和排版上都有诸多不清晰和不一致之处，使得编码和调试时很不舒服。\n\n- 命名不统一：大部分线路名采用模块名作为前缀以指示归属，但仍有部分代码存在问题。线路名称中有些前缀后加`_`区别，有些不加，命名不一致。模块对内和对外的线路命名可以不同，但有时加前缀，有时不加，难以一眼确定线路归属，令人困惑。\n\n- 结构不清晰：流水线寄存器本来应当与各个执行阶段在同一个级别之上，按顺序依次传递数据。但是，代码中将流水线寄存器放在执行阶段模块的代码之中，这正是使得变量命名混乱和代码逻辑不清晰的根源。同时，甚至有将某个多路选择器逻辑放置在流水线寄存器模块代码之中的做法，这令我很难接受。\n\n因此，我选择了自己重新实现。\n\n至于选择开源，是想要给这门课程的实验提供一份清晰且一致的代码实现，也希望能够有助于同学们更加直观地理解流水线 CPU 的具体实现。\n\n\u003e 希望前人所走过的弯路后人都不必再走，这是我对开源的信念之一。\n\n## 特点\n\n- 基于课程提供的电路原理图，符合课程要求和实践。原线路命名与项目中线路命名对应关系在执行阶段模块的声明中以注释的方式给出。\n\n    ![流水线 CPU 原理图](assets/readme/schematic.png)\n\n- 使用 VGA 显示大量调试信息。\n\n    得益于 VGA 较大的信息量，可以将许多有利于调试或教学的信息都打印在屏幕上实时更新。利用一个组合电路的反汇编器，可以看到当前阶段正在执行指令的汇编源代码。VGA 模块中控制显示相关的长段代码也由 Python 脚本生成，可以通过读取用文本文档记录的设计，快速进行修改。\n\n    ![VGA 调试设计图](assets/readme/debugger-design.png)\n\n    ![VGA 调试实现效果](assets/readme/debugger.jpg)\n\n- 合理的代码组织方式。\n\n    在 CPU 模块之下，PC、各个流水线寄存器和各个执行阶段模块依次连接，尽力实现代码组织的合理和明确。\n\n    ![CPU 代码组织结构](assets/readme/organization.png)\n\n- 统一的代码风格和排版。\n\n    经过权衡，项目代码采用了较长的命名，是为了将原本意义不明显、需要常常查看注释或原理图的变量名称，转变为清晰、不容易出错的名称，由此项目编码过程中未出现过代码逻辑错误。\n\n    命名规则的统一使得线路功能和归属清晰可靠，而代码中的缩进、空行分块和前后顺序等排版也尽量追寻体现代码之间的逻辑关系，便于阅读和维护。\n\n    项目代码始终尽量采用推荐的 Verilog 实践，例如新的模块声明方式。\n\n- 自动生成部分模块和模块连线代码。\n\n    得益于统一的命名风格和代码组织，流水线寄存器模块和各模块之间连线的代码可以按照特定规则生成。本项目采用 Python 脚本完成了数百行的代码生成，避免大量繁杂和容易出错的工作，同时由此以后修改接口时也可以更为简单。\n\n    ![流水线寄存器代码生成脚本](assets/readme/code-generation.png)\n\n    本项目中大部分代码逻辑都在 `*Stage.v` 中，而 `*Registers.v` 和 `Cpu.v` 均为生成的代码。\n\n## 许可\n\n```\nCopyright (c) 2016 Zhang Hai \u003cdreaming.in.code.zh@gmail.com\u003e\n\nThis program is free software: you can redistribute it and/or modify\nit under the terms of the GNU General Public License as published by\nthe Free Software Foundation, either version 3 of the License, or\n(at your option) any later version.\n\nThis program is distributed in the hope that it will be useful, but\nWITHOUT ANY WARRANTY; without even the implied warranty of\nMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\nGeneral Public License for more details.\n\nYou should have received a copy of the GNU General Public License\nalong with this program.  If not, see\n\u003chttp://www.gnu.org/licenses/\u003e.\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fzhanghai%2Farchexp","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fzhanghai%2Farchexp","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fzhanghai%2Farchexp/lists"}