{"id":792,"slug":"riscv","name":"RISC-V","short_description":"RISC-V (risk-five) is an open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC).","url":"https://github.com/topics/riscv","github_count":1377,"created_by":null,"logo_url":"https://explore-feed.github.com/topics/riscv/riscv.png","released":null,"wikipedia_url":"https://en.wikipedia.org/wiki/riscv","related_topics":[],"aliases":["risc-v","riscv-cpu","riscv-core"],"github_url":null,"content":"\u003cp\u003eUnlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.\u003c/p\u003e\n\n\u003cp\u003eNotable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.\u003c/p\u003e\n","created_at":"2024-07-29T13:56:57.934Z","updated_at":"2026-06-25T00:23:02.289Z","topic_url":"https://awesome.ecosyste.ms/api/v1/topics/riscv","html_url":"https://awesome.ecosyste.ms/topics/riscv","projects_url":"https://awesome.ecosyste.ms/api/v1/projects?keyword=riscv","lists_url":"https://awesome.ecosyste.ms/api/v1/lists?topic=riscv"}