Ecosyste.ms: Awesome

An open API service indexing awesome lists of open source software.

awesome-neuromorphic-hw

Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.
https://github.com/open-neuromorphic/awesome-neuromorphic-hw

  • [IEEE-Proc
  • [IEEE-JETCAS
  • [IEEE-CICC
  • [IEEE-JETCAS - Memory Computing Cores by Direct Minimization of the Matrix-Vector Multiplication Error. [__`asic`__][__`imc`__][__`memristive`__][__`mixed-signal`__]
  • [IEEE-JETCAS - nm with ReRAM Synapses and Digital Neurons. [__`asic`__][__`imc`__][__`memristive`__][__`mixed-signal`__]
  • [IEEE-JETCAS - CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator with Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Application [__`asic`__][__`imc`__][__`memristive`__]
  • [IEEE-TVLSI - Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory [__`asic`__][__`imc`__]
  • [IEEE-TED - MRAM Crossbar Array [__`mixed-signal`__][__`asic`__][__`imc`__][__`memristive`__]
  • [ArXiv - SE2: a scalable multi-core dynamic neuromorphic asynchronous spiking neural network processor [__`mixed-signal`__][__`asic`__][__`async`__]
  • [ArXiv - Performance Spiking Neural Network with a Spatiotemporal FPGA Accelerator [__`digital`__][__`fgpa`__]
  • [IEEE-JETCAS - DNN V2: Complementary Deep-Neural-Network Processor with Full-Adder/OR-based Reduction Tree and Reconfigurable Spatial Weight Reuse [__`digital`__][__`asic`__]
  • [IEEE-TVLSI - Throughput and Reconfigurable Hardware Accelerator for Spiking Neural Networks. [__`digital`__][__`fpga`__]
  • [IEEE-ISCAS - source`__][[Code](https://github.com/sfmth/OpenSpike)]
  • [ArXiv - - A Neuromorphic Processor with 7.29G TSOP2/mm2Js Energy-Throughput Efficiency. [__`digital`__][__`asic`__]
  • [IEEE-TCAD
  • [ArXiv
  • [IEEE-JSSC - Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit. [__`digital`__][__`asic`__]
  • [IEEE-ISSCC - DNN: A 24.5-85.8TOPS/W Complementary-Deep-Neural-Network Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation. [__`digital`__][__`asic`__]
  • [IEEE-CICC - Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology. [__`digital`__][__`asic`__][__`in-memory-computing`__]
  • [IEEE-ISCAS - Network Computing. [__`digital`__][__`asic`__]
  • [IEEE-JSSC - CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital–Analog Networks. [__`digital`__][__`asic`__][__`mixed-signal`__]
  • [IEEE-TCAS-II - Encoded Spiking Neural Networks in 7nm CMOS Technology. [__`digital`__][__`asic`__]
  • [ArXiv - SOI crossbar output circuit for low power analog SNN inference with eNVM synapses. [__`mixed-signal`__][__`memristive`__]
  • [IEEE-TBioCAS - mm2 6.2-pJ/SOP Online Learning Multi-Topology SNN Processor with Unified Computation Engine in 40-nm CMOS. [__`digital`__][__`asic`__]
  • [IEEE-TCAS-II - Gesture with WS-LOS Dataflow and Sparse Methods. [__`digital`__][__`asic`___]
  • [IEEE-ISSCC - I: A 28nm 1.5pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-O.1 μJ/Sample On-Chip Learning for Edge-AI Applications. [__`digital`__][__`asic`__][__`async`__]
  • [IEEE-TCAD - Aware Training Accelerator for Spiking Neural Networks [__`digital`__][__`asic`__]
  • [IEEE-COOL-CHIPS - NPU: Complementary Online Learning Neural Processing Unit with CNN-SNN Heterogeneous Core and Event-driven Backpropagation.
  • [IEEE-TCAS-I - nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40- μ s Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique. [__`async`__][__`asic`__][__`imc`__][__`mixed-signal`__]
  • [IEEE-AICAS - chip always-on learning in spiking neural networks. [__`asic`__][__`mixed-signal`__][__`on-chip-learning`__]
  • [ArXiv - Based Routers for Asynchronous Neuromorphic Systems. [__`mixed-signal`__][__`memristive`__]
  • [IEEE-ISSCC - mm2 Task-Agnostic Spiking Recurrent Neural Network Processor Enabling On-Chip Learning over Second-Long Timescales. [__`digital`__][__`asic`__][__`open-source`__][[Code](https://github.com/chfrenkel/ReckON)]
  • [DATE - Proportional Digital Accelerator for Sparse Event-Based Convolutions. [__`digital`__][__`asic`__][__`open-source`__][[Code](https://github.com/pulp-platform/sne)]
  • [IEEE-TCAS-I
  • [IEEE-TCAD - Temporal Workload Balance [__`digital`__][__`fpga`__]
  • [IEEE/ACM-DAC - oriented dataflow and architecture [__`digital`__][__`asic`__]
  • [IEEE-JSSC - Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique. [__`digital`__][__`asic`__][__`async`__][__`imc`__]
  • [IEEE-Access - Signal Spiking Neural Network Processor With 8-bit Synaptic Weight On-Chip Learning That Operates in the Continuous-Time Domain. [__`mixed-signal`__][__`online-learning`__][__`asic`__]
  • [Frontiers - Driven and Fully Synthesizable Architecture for Spiking Neural Networks. [__`digital`__][__`asic`__][__`async`__]
  • [ArXiv
  • [IEEE-TCAS-I - mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router. [__`digital`__][__`asic`__]
  • [IEEE-LSSC - nm Digital Compute-in-Memory Macro With Fused Weights and Membrane Potential for Spike-Based Sequential Learning Tasks. [__`digital`__][__`asic`__]
  • [IEEE-TVLSI
  • [ACM-TRTS - HiAccel/SyncNN)]
  • [IEEE-FPL - FPGA`__]
  • [ACM-FPGA
  • [IEEE-TCAS-I - Efficient SNN Processor With Adaptive Clock/Event-Driven Computation Scheme and Online Learning [__`digital`__][__`fpga`__]
  • [IEEE-A-SSCC - On, Sub-300-nW, Event-Driven Spiking Neural Network based on Spike-Driven Clock-Generation and Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device. [__`digital`__][__`asic`__][__`async`__]
  • [IEEE-JSSC - based and continuous neural computation. [__`digital`__][__`asic`__]
  • [IEEE-RAW - RCL/RANC)]
  • [IEEE-A-SSCC
  • [IEEE-ISSCC - RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. [__`mixed-signal`__]
  • [Springer-JCST - Programmable Gate Array [__`digital`__][__`fpga`__]
  • [IEEE/ACM-ISCA
  • [IEEE/ACM-ICCAD
  • [IEEE-JSSC - nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics. [__`mixed-signal`__][__`asic`__]
  • [IEEE-TBioCAS - mm2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS. [__`digital`__][__`asic`__][__`open-source`__][[ODIN](https://github.com/ChFrenkel/ODIN)][[TinyODIN](https://github.com/ChFrenkel/tinyODIN)]
  • [IEEE-TBioCAS - nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning. [__`digital`__][__`asic`__]
  • [IJSSC - Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS. [__`digital`__][__`asic`__]
  • [IEEE-CICC - Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS. [__`digital`__][__`asic`__]
  • [IEEE-JSSC - nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback. [__`digital`__][__`asic`__]
  • [IEEE-ISVLSI - based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation. [__`mixed-signal`__]
  • [IEEE-MICRO - Chip Learning. [__`digital`__][__`asic`__]
  • [IEEE-TBioCAS - signal`__]
  • [IEEE-JPROC - Signal Neuromorphic Architecture With a Dynamical Systems-Based Programming Model. [__`mixed-signal`__][[Thesis](https://stacks.stanford.edu/file/druid:sg377qc5355/thesis_toplevel-augmented.pdf)]
  • [IEEE-ISVLSI - chip learning and classification in 40nm CMOS. [__`mixed-signal`__]
  • [IEEE-TCAD
  • [Frontiers - line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses. [__`mixed-signal`__][__`async`__]
  • [IEEE-ISVLSI - driven neuromorphic object recognition processor with on-chip learning.
  • [IEEE-TBioCAS - Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits.
  • [IEEE-BioCAS - neuron 73-Mevents/s 22-pJ/event asynchronous micro-pipelined integrate-and-fire array transceiver.[__`async`__]
  • [IEEE-JPROC - Analog-Digital Multichip System for Large-Scale Neural Simulations. [__`mixed-signal`__]
  • [IEEE-TVLSI - Driven FPGA-Based Spiking Network Accelerator. [__`digital`__][__`fpga`__]
  • [IEEE-MICRO - W 18-Core System-onChip for Massively-Parallel Neural Network Simulation. [__`digital`__][__`asic`__][__`async`__]
  • [IEEE-CICC
  • [IEEE-ISCAS - scale neuromorphic hardware system for large-scale neural modeling. [__`mixed-signal`__]