Benchmarks

Low-Precision Training and States

• MQBench: Towards Reproducible and Deployable Model Quantization Benchmark
• Evaluating Quantized Large Language Models - nics/qllm-eval) · Scholar | Weights, activations + KV cacheEvaluates 11 model families on basic NLP, emergent abilities, trustworthiness, dialogue and long-context tasks. |
• An empirical study of LLaMA3 quantization: from LLMs to MLLMs - Quantization) · Scholar | LLMs + multimodalExamines low-bit behavior across LLaMA3 language and multimodal models. |
• An Empirical Study of Qwen3 Quantization - ML/Qwen3-Quantization) · Scholar | Dense + MoE LLMsStudies quantization across Qwen3 model sizes, architectures and reasoning settings. |
• RobustMQ: Benchmarking Robustness of Quantized Models

• [Paper
• [Paper - Quantization)]
• [Paper - ML/Qwen3-Quantization)]
• [Paper
• [Paper
• [Paper - Quantization)]
• [Paper

Books

2014

• Efficient Processing of Deep Neural Networks - Hsin Chen, Tien-Ju Yang, Joel S. Emer2020 | Reduced precision in the wider context of data movement, accelerators and hardware–algorithm co-design. |
• Vector Quantization and Signal Compression
• Machine Learning Systems - access online textbook | Model compression and numerical precision within end-to-end ML systems engineering. |
• Efficient Processing of Deep Neural Networks - Hsin Chen, Tien-Ju Yang, Joel S. Emer2020 | Reduced precision in the wider context of data movement, accelerators and hardware–algorithm co-design. |

2015

• Quantization and Fast Inference: A practitioner’s guide to efficient AI

Papers

2015

• [ICML
• [NeurIPS
• [arXiv

2016

• [CVPR - wu/quantized-cnn)
• [arXiv - Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients [code]
• [ECCV - Net: ImageNet Classification Using Binary Convolutional Neural Networks [code]
• [ICASSP - point Performance Analysis of Recurrent Neural Networks
• [NeurIPS - 1 [code]
• [NeurIPS - chris/caffe-twns)]

2017

• [CVPR - wave Gaussian Quantization [code]
• [CVPR
• [arXiv - Source Binary Neural Network Implementation Based on MXNet [code]
• [FPGA
• [ICASSP - point optimization of deep neural networks with adaptive step size retraining
• [ICCV - cnn-landmarks)]
• [ICCV - Order Residual Quantization
• [ICLR - Precision Weights [code]
• [ICLR - aware Binarization of Deep Networks [code]
• [ICLR - Sharing for Neural Network Compression
• [ICLR - ternary-quantization)]
• [IPDPSW - Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA
• [InterSpeech
• [JETC - Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks
• [MWSCAS
• [NeurIPS - Binary-Convolution-Network)]
• [Neurocomputing - BNN: Binarized neural network on FPGA
• [arXiv - Precision Architecture for Inference of Convolutional Neural Networks [code]
• [arXiv - Grained Quantization

2018

• [AAAI
• [AAAI
• [CAAI
• [CVPR - bitwidth Weights and Activations
• [CVPR - error-aware quantization for low-bit deep neural networks
• [CVPR
• [CVPR - Arithmetic-Only Inference
• [CVPR
• [CVPR - bitwidth Convolutional Neural Networks
• [CVPR - Step Quantization for Low-bit Neural Networks
• [arXiv
• [arXiv
• [ECCV - Real Net: Enhancing the Performance of 1-bit CNNs With Improved Representational Capability and Advanced Training Algorithm [code]
• [ECCV - Nets: Learned Quantization for Highly Accurate and Compact Deep Neural Networks [code]
• [ECCV
• [ECCV
• [ECCV - Binary Decomposition
• [FCCM
• [FPL
• [ICLR
• [ICLR - Precision Network Accuracy
• [ICLR - aware Weight Quantization of Deep Networks [code]
• [ICLR
• [ICLR - Precision Networks
• [IEEE J. Solid-State Circuits - Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W
• [IJCAI
• [IJCAI
• [IJCNN
• [IPDPS
• [MM - Time Low-Power Inference of Binary Neural Networks on CPUs
• [NCA - based accelerators for convolutional neural networks
• [NeurIPS - bit training of neural networks [code]
• [NeurIPS - bit Floating Point Numbers
• [Res Math Sci
• [TCAD - fJ/op Binary Neural Network Inference
• [TRETS - R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
• [TVLSI - Efficient Architecture for Binary Weight Convolutional Neural Networks
• [arXiv - quantization)]
• [arXiv - xnor/BMXNet-v2)]

2019

• [AAAI
• [AAAI - bit CNNs via Discrete Back Propagation
• [APCCAS
• [BMVC
• [BMVC - Net++: Improved Binary Neural Networks
• [CVPR
• [CVPR
• [CVPR - bit DCNNs with Circulant Back Propagation
• [CVPR
• [CVPR - Aware Automated Quantization with Mixed Precision [code]
• [CVPR - Wise Interactions for Binary Convolutional Neural Networks
• [CVPR
• [CVPR - quantization-networks)]
• [CVPR
• [CVPR - Map Sparsity Through Low-Bit Quantization
• [CVPR
• [arXiv - xnor/BMXNet-v2)]
• [arXiv
• [arXiv
• [arXiv
• [arXiv - bit DCNNs
• [arXiv - Ensemble Template for Accurate Binary Convolutional Neural Networks
• [FPGA - Efficient Binarized Neural Network Inference on FPGA
• [GLSVLSI
• [ICCV - bit cnns
• [ICCV - Free Quantization Through Weight Equalization and Bias Correction [code]
• [ICCV - Precision and Low-Bit Neural Networks
• [ICCV
• [ICCV - Precision
• [ICCV
• [ICIP - xnor/BMXNet-v2)]
• [ICLR
• [ICLR
• [ICML - Bit Quantization of Transformer Neural Machine Language Translation Model
• [ICUS
• [IEEE J. Emerg. Sel. Topics Circuits Syst. - Chip Systolically Scalable Binary-Weight CNN Inference Engine
• [IEEE J. Solid-State Circuits - Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width
• [IEEE JETC
• [IEEE TCS.I - Chip Memory
• [IEEE TCS.I - RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays
• [IJCAI
• [IJCAI - Efficient Hashing with Minimizing Quantization Loss
• [ISOCC
• [MDPI Electronics
• [NeurIPS
• [NeurIPS - bnn-optimization)]
• [NeurIPS - differentiable Quantization [code]
• [NeurIPS
• [NeurIPS
• [NeurIPS
• [NeurIPS
• [RoEduNet
• [SiPS
• [TMM
• [TMM - Modal Hashing
• [VLSI-SoC - Efficient Execution of Binary Neural Networks Using Resistive Memories
• [arXiv - CV/dabnn)]
• [arXiv
• [arXiv - aware Knowledge Distillation
• [arXiv - Binarizing Networks
• [arXiv
• [paper

2020

• [CVPR - Net)]
• [PR
• [AAAI - BERT: Hessian Based Ultra Low Precision Quantization of BERT
• [ACL
• [COOL CHIPS - DRAM Accelerator Architecture for Binary Neural Network
• [CVPR - han-lab/apq)]
• [CVPR
• [CVPR - Point Back-Propagation Training
• [CVPR
• [CVPR - Bit Quantization Needs Good Distribution
• [CVPR - Bit Face Recognition
• [arXiv
• [DATE - based computing systems
• [DATE
• [DATE - Accelerated Binary Neural Network Inference Engine for Mobile Phones
• [ECCV
• [ECCV
• [ECCV - bitwidth Data Free Quantization [code]
• [ECCV
• [ECCV - 4-bit MobileNet Models
• [ECCV
• [ECCV
• [EMNLP
• [EMNLP - aware Ultra-low Bit BERT [code]
• [ICASSP
• [ICET - Efficient Bagged Binary Neural Network Accelerator
• [ICLR - K1m/BinaryDuo)]
• [ICLR
• [ICLR
• [ICLR - research-code/tree/master/mixed-precision-dnns)]
• [ICLR - to-Binary Convolutions
• [ICML - Scale Inference with Anisotropic Vector Quantization
• [ICML - bit quantization through learnable offsets and better initialization
• [ICML
• [ICML - Training Quantization
• [IEEE Access - Efficient and High Throughput in-Memory Computing Bit-Cell With Excellent Robustness Under Process Variations for Binary Neural Network
• [IEEE TCS.I - Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array
• [IEEE TCS.II - Efficient Inference Accelerator for Binary Convolutional Neural Networks
• [IEEE Trans. Electron Devices
• [IEEE Trans. Magn - Memory Binary Neural Network Accelerator
• [IJCAI - NAS: Child-Parent Neural Architecture Search for Binary Neural Networks
• [IJCAI - width Deep Neural Networks
• [IJCAI
• [IJCAI - bit Multiply-Accumulate Operations
• [IJCAI
• [IJCAI - bit Integer Inference for the Transformer Model
• [IJCV
• [ISCAS - Level Binarized Recurrent Neural Network for EEG Signal Classification
• [ISQED - ASU/BNNPruning)]
• [MICRO - Based NLP Models for Low Latency and Energy Efficient Inference
• [MLST
• [NN - performance and large-scale deep neural networks with full 8-bit integers
• [NeurIPS - Parallel SGD [code]
• [NeurIPS