https://github.com/riscv-boom/riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine
https://github.com/riscv-boom/riscv-boom

berkeley boom chisel riscv riscv-boom rocket-chip rtl scala

Last synced: 16 days ago
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SonicBOOM: The Berkeley Out-of-Order Machine

• Host: GitHub
• URL: https://github.com/riscv-boom/riscv-boom
• Owner: riscv-boom
• License: bsd-3-clause
• Created: 2014-01-21T17:18:10.000Z (over 10 years ago)
• Default Branch: master
• Last Pushed: 2024-05-17T23:16:26.000Z (about 1 month ago)
• Last Synced: 2024-05-18T20:47:15.987Z (about 1 month ago)
• Topics: berkeley, boom, chisel, riscv, riscv-boom, rocket-chip, rtl, scala
• Language: Scala
• Homepage:
• Size: 12.1 MB
• Stars: 1,609
• Watchers: 82
• Forks: 401
• Open Issues: 102
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Lists

• awesome-stars - riscv-boom/riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine (Scala)
• StarryDivineSky - riscv-boom/riscv-boom - V 处理器.一个可合成和可参数化的开源 RV64GC RISC-V 内核，用[Chisel](https://chisel.eecs.berkeley.edu/)硬件构造语言编写。其重点是为研究创建一个高性能、可综合和可参数化的核心。当前版本的 BOOM 微架构（[SonicBOOM，或 BOOMv3](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf)）与商用高性能无序内核具有竞争力，达到 6.2 CoreMarks/MHz。 (CPU RISC-V / 网络服务_其他)
• awesome-riscv - boom - of-order|FPGA,ASIC|BSD,Apache-2| (Open Source Core Implementations)

README

        
![](docs/figures/evolution.png)

The Berkeley Out-of-Order RISC-V Processor [![CircleCI](https://circleci.com/gh/riscv-boom/riscv-boom.svg?style=svg)](https://circleci.com/gh/riscv-boom/riscv-boom)

====================================================================================================================================================================

The Berkeley Out-of-Order Machine (BOOM) is a synthesizable and parameterizable open source RV64GC RISC-V core written in the [Chisel](https://chisel.eecs.berkeley.edu/) hardware construction language.

Created at the University of California,

Berkeley in the [Berkeley Architecture Research](https://bar.eecs.berkeley.edu/) group, its focus is to create a high performance, synthesizable, and parameterizable core for architecture research.

The current version of the BOOM microarchitecture ([SonicBOOM, or BOOMv3](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf)) is performance competitive with commercial high-performance out-of-order cores, achieving 6.2 CoreMarks/MHz.

![](docs/figures/uarch.png)

Feature | BOOM

--- | ---

ISA | RISC-V (RV64GC)

Synthesizable |√

FPGA |√

Parameterized |√

IEEE 754 Floating Point |√

Atomics |√

Caches |√

Virtual Memory |√

Boots Linux |√

Runs SPEC |√

CoreMark/MHz |6.2

## IMPORTANT: Using BOOM

This repository is **NOT A SELF-RUNNING** repository. To instantiate a BOOM core, please use the

[Chipyard](https://github.com/ucb-bar/chipyard) SoC generator.

The current hash of Chipyard that works with this repository is located in the `CHIPYARD.hash`

file in the top level directory of this repository. This file is mainly used for CI purposes, since

Chipyard should follow the correct version of rocket-chip. For most users, you should be able to

clone Chipyard separately and follow the default Chipyard instructions (without having to use the `.hash` file).

While BOOM is primarily ASIC-optimized, it is also usable on FPGAs.

Chipyard provides infrastructure and documentation for deploying BOOM on AWS F1 FPGAs through FireSim.

## Documentation and Information

Please check out the BOOM website @ https://boom-core.org for the most up-to-date information.

It contains links to the mailing lists, documentation, design spec., publications and more!

If you use BOOMv3 in your published work, please cite BOOM as

```

@article{zhaosonicboom,

  title={SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine},

  author={Zhao, Jerry and Korpan, Ben and Gonzalez, Abraham and Asanovic, Krste},

  booktitle={Fourth Workshop on Computer Architecture Research with RISC-V},

  year={2020},

  month={May}

}

```

**Website:** (www.boom-core.org)

**Mailing List** (https://groups.google.com/forum/#!forum/riscv-boom)

## Disclaimer!

BOOM is a work-in-progress and remains in active development.

## Contributing

Please see [CONTRIB\_AND\_STYLE.md](/CONTRIB_AND_STYLE.md)