https://github.com/SI-RISCV/e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
https://github.com/SI-RISCV/e200_opensource

china core cpu nuclei risc-v ultra-low-power verilog

Last synced: 13 days ago
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Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

• Host: GitHub
• URL: https://github.com/SI-RISCV/e200_opensource
• Owner: SI-RISCV
• License: apache-2.0
• Archived: true
• Created: 2017-07-27T15:38:44.000Z (almost 7 years ago)
• Default Branch: master
• Last Pushed: 2021-03-24T09:38:39.000Z (over 3 years ago)
• Last Synced: 2024-02-28T19:36:12.084Z (4 months ago)
• Topics: china, core, cpu, nuclei, risc-v, ultra-low-power, verilog
• Language: Verilog
• Homepage: https://github.com/riscv-mcu/e203_hbirdv2
• Size: 90.1 MB
• Stars: 2,493
• Watchers: 227
• Forks: 988
• Open Issues: 33
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Lists

• awesome-stars - SI-RISCV/e200_opensource - Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2 (Verilog)
• awesome-stars - e200_opensource - The Ultra-Low Power RISC Core (Verilog)
• awesome-RISCV-Cores - GitHub
• awesome-stars - SI-RISCV/e200_opensource - Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2 (Verilog)