https://github.com/bluespec/Piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
https://github.com/bluespec/Piccolo

Last synced: 16 days ago
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RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

• Host: GitHub
• URL: https://github.com/bluespec/Piccolo
• Owner: bluespec
• License: apache-2.0
• Created: 2018-05-29T20:35:53.000Z (about 6 years ago)
• Default Branch: master
• Last Pushed: 2022-01-23T23:41:45.000Z (over 2 years ago)
• Last Synced: 2024-02-28T19:35:59.836Z (4 months ago)
• Language: Verilog
• Size: 11.9 MB
• Stars: 292
• Watchers: 24
• Forks: 46
• Open Issues: 16

Lists

• awesome-stars - bluespec/Piccolo - RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT) (Verilog)
• awesome-stars - bluespec/Piccolo - RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT) (Verilog)
• awesome-riscv - Piccolo@bluespec - stage in-order|ASIC|Apache| (Open Source Core Implementations)