https://github.com/dawsonjon/Chips-2.0

FPGA Design Suite based on C to Verilog design flow.
https://github.com/dawsonjon/Chips-2.0

Last synced: 3 months ago
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FPGA Design Suite based on C to Verilog design flow.

• Host: GitHub
• URL: https://github.com/dawsonjon/Chips-2.0
• Owner: dawsonjon
• License: mit
• Created: 2011-11-26T11:11:04.000Z (over 12 years ago)
• Default Branch: master
• Last Pushed: 2019-04-05T16:27:04.000Z (about 5 years ago)
• Last Synced: 2024-03-01T02:21:46.553Z (4 months ago)
• Language: Python
• Homepage: www.pyandchips.org
• Size: 7.49 MB
• Stars: 226
• Watchers: 21
• Forks: 47
• Open Issues: 19
• Metadata Files:
  • Readme: README.rst
  • License: COPYING.txt

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• alex-mikhalev-awesome-stars - Chips-2.0 - FPGA Design Suite based on C to Verilog design flow. (Python)

README

        
.. image:: https://travis-ci.org/dawsonjon/Chips-2.0.svg?branch=master

    :target: https://travis-ci.org/dawsonjon/Chips-2.0`

.. image:: https://readthedocs.org/projects/chips-20/badge/?version=latest

    :target: https://readthedocs.org/projects/chips-20/badge/?version=latest

Chips - 2.0

===========

*Chips* is a high level, FPGA design tool inspired by *Python*.

Try it out

----------

Why not try the `Chips `_ web app. 

Design components in C, design FPGAs in Python

----------------------------------------------

In Chips, a design resembles a network of computers implemented in a single

chip. A chip consists of many interconnected components operating in parallel.

Each component acts like a computer running a C program. 

Components communicate with each other sending messages across buses. The

design of a chip - the components and the connections between them - is carried

in Python. 

Chips come in three parts:

1. A Python library to build and simulate chips by connecting together digital components using high speed buses.

2. A collection of ready made digital components.

3. A C-to-hardware compiler to make new digital components in the C programming language.

A quick example

---------------

::

        from chips.api.api import *

        

        #create a new chip

        chip = Chip("knight_rider")

        #define a component in C

        scanner = Component(C_file = """

            /* Knight Rider */

            int leds = output("leds");

            void main(){

                unsigned shifter = 1;

                while(1){

                    while(shifter != 0x80){

                        fputc(shifter, leds);

                        shifter <<= 1;

                        wait_clocks(5000000);

                    }

                    while(shifter != 0x01){

                        fputc(shifter, leds);

                        shifter >>= 1;

                        wait_clocks(5000000);

                    }

                }

            }

        """, inline=True)

        #capture simulation output in Python

        scanner_output = Response(chip, "scanner", "int")

        

        #add scanner to chip and connect

        scanner(chip, inputs = {}, outputs = {"leds":scanner_output})

        #generate synthesisable verilog code

        chip.generate_verilog()

        #run simulation in Python

        chip.simulation_reset()

        while len(scanner_output) < 16:

            chip.simulation_step()

        #check the results

        print list(scanner_output)

..        

Work at a higher level of abstraction 

-------------------------------------

In Chips, the details of gates, clocks, resets, finite-state machines and

flow-control are handled by the tool, this leaves the designer free to think

about the architecture and the algorithms. This has some benefits:

+ Designs are simpler.

+ Simpler designs take much less time to get working.

+ Simpler designs are much less likely to have bugs.

With Chips the batteries *are* included 

---------------------------------------

With traditional Hardware Description Languages, there are many restrictions on

what can be translated into hardware and implemented in a chip.

With Chips almost all legal code can be translated into hardware. This includes

division, single and double precision IEEE floating point, maths functions,

trig-functions, timed waits, pseudo-random numbers and recursive function

calls.

Python is a rich verification environment

-----------------------------------------

Chips provides the ability to simulate designs natively in Python.  Python is

an excellent programming language with extensive libraries covering many

application domains. This makes it the perfect environment to verify a chip.

`NumPy `_ , `SciPy `_  and

`MatPlotLib `_  will be of interest to

engineers, but that's just the `start `_ .

Under the hood

--------------

Behind the scenes, Chips uses some novel techniques to generate compact and

efficient logic - a hybrid of software and hardware. 

Not only does the compiler translate the C code into CPU instructions, it also

generates a customised pipelined RISC CPU on the fly. The CPU provides the

optimal instruction set for any particular C program.

By minimising the logic required to perform each concurrent task, designers can

reduce power and area or cost. Performance gains can be achieved by increasing

the number of concurrent tasks in a single device (tens in a small device to

around a thousand or more large device).

While the code generated by chips is compact and efficient, die hard FPGA

designers will be pleased to know that they can still hand craft performance

critical data paths if they need to. There are even a few hand crafted

components thrown in!

Install from github

-------------------

::

        $ git clone --recursive https://github.com/dawsonjon/Chips-2.0.git

        $ cd Chips-2.0

        $ sudo python setup install

Install from PyPi

-----------------

::

        $ pip-install chips