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https://github.com/ultraembedded/core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
https://github.com/ultraembedded/core_ddr3_controller
Last synced: 3 months ago
JSON representation
A DDR3 memory controller in Verilog for various FPGAs
- Host: GitHub
- URL: https://github.com/ultraembedded/core_ddr3_controller
- Owner: ultraembedded
- Created: 2020-07-14T22:30:42.000Z (almost 4 years ago)
- Default Branch: master
- Last Pushed: 2021-10-10T16:10:37.000Z (over 2 years ago)
- Last Synced: 2024-02-28T11:31:39.092Z (4 months ago)
- Language: Verilog
- Size: 232 KB
- Stars: 275
- Watchers: 18
- Forks: 74
- Open Issues: 1
Lists
- awesome-opensource-hardware - core_ddr3_controller
- awesome-stars - ultraembedded/core_ddr3_controller - A DDR3 memory controller in Verilog for various FPGAs (Verilog)
- awesome-cuda-tensorrt-fpga - ultraembedded/core_ddr3_controller
- awesome-opensource-hardware-repos - core_ddr3_controller