https://github.com/waviousllc/wav-wlink-hw

Wavious Wlink
https://github.com/waviousllc/wav-wlink-hw

Last synced: 3 months ago
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Wavious Wlink

• Host: GitHub
• URL: https://github.com/waviousllc/wav-wlink-hw
• Owner: waviousllc
• License: apache-2.0
• Created: 2021-09-23T17:24:12.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2021-10-28T18:22:40.000Z (over 2 years ago)
• Last Synced: 2024-01-17T20:46:41.485Z (6 months ago)
• Language: Scala
• Size: 615 KB
• Stars: 8
• Watchers: 1
• Forks: 3
• Open Issues: 1
• Metadata Files:
  • Readme: README.rst
  • License: LICENSE

Lists

• awesome-opensource-hardware - wav-wlink-hw
• awesome-opensource-hardware-repos - wav-wlink-hw

README

        
Wavious Wlink

========================

The Wavious Wlink defines a low latency, packet based, layered architecture for communicating between two chiplets. Wlink

exposes on-chip application protocols and converts these for transmission across chiplets via various physical layer

implementations. Wlink is highly configurable, allowing users to communicate between chiplets utilizing current and

future on-chip application protocols. Wlink allows user to define implementation specific physical layers without

the need to change RTL for the controller infrastructure

Documentation

---------------

https://wlink.readthedocs.io/en/latest/

Project Requirements

---------------------

* make

* java

* sbt

* icarus verilog (if running simulations)

  

  * Please use version 11.0 or later

*gtkwave with compression packages for viewing waves

Getting Started

------------------

::

  

  git clone 

  cd wav-wlink-hw

  git submodule update --init --recursive 

Create your first Wlink Design!

--------------------------------

If this is your first run, the initial build may take 5-10 minutes depending on your 

CPU setup.

::

  

  make wlink 

  

Will generate a simple wlink design that has a 1lane GPIO Phy and 32bit AXI ports.

Output RTL will be located in the wav.wlink.AXI32bit1LaneWlinkTestConfig/ directory.

Wlink.v is top level RTL file.

Run a simulation!

--------------------------------

::

  

  make testharness

  

Will generate the WlinkSimpleTestHarness that instantiates two Wlink instances back to

back. The test harness will generate some random AXI reads/writes and compare the data.

You can run the simple testbench by doing the following:

::

  cd verif/

  ./run.sh -o ../wav.wlink.AXI32bit1LaneWlinkTestConfig/

See an issue? Have a question?

--------------------------------

Feel free to submit an issue! Please note that we are a small team so responses may not be immediate.