https://github.com/ultraembedded/core_axi_cache

128KB AXI cache (32-bit in, 256-bit out)
https://github.com/ultraembedded/core_axi_cache

Last synced: 2 months ago
JSON representation

128KB AXI cache (32-bit in, 256-bit out)

• Host: GitHub
• URL: https://github.com/ultraembedded/core_axi_cache
• Owner: ultraembedded
• License: bsd-3-clause
• Created: 2021-05-10T19:35:39.000Z (about 3 years ago)
• Default Branch: main
• Last Pushed: 2021-05-10T19:43:37.000Z (about 3 years ago)
• Last Synced: 2024-02-28T11:31:39.061Z (4 months ago)
• Language: Verilog
• Size: 18.6 KB
• Stars: 25
• Watchers: 4
• Forks: 5
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Lists

• awesome-opensource-hardware - core_axi_cache
• awesome-opensource-hardware-repos - core_axi_cache

README

        
### AXI Cache (32-bit input, 256-bit output)

Github:   [https://github.com/ultraembedded/core_axi_cache](https://github.com/ultraembedded/core_axi_cache)

#### Features

* This cache instance is 2 way set associative.

* The total size of 128KB.

* The replacement policy is a limited pseudo-random scheme (between lines, toggling on line thrashing).

* The cache is a write-back cache, with allocate on read and write.

* 32-byte lines

* 32-bit AXI4 input, 256-bit AXI4 output.

* Does not support narrow bursts (Axsize != 2).