https://github.com/StanfordAHA/lake

Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.
https://github.com/StanfordAHA/lake

Last synced: 2 months ago
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Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.

• Host: GitHub
• URL: https://github.com/StanfordAHA/lake
• Owner: StanfordAHA
• License: bsd-3-clause
• Created: 2019-07-31T05:45:32.000Z (almost 5 years ago)
• Default Branch: master
• Last Pushed: 2024-04-17T05:07:54.000Z (2 months ago)
• Last Synced: 2024-04-23T00:13:10.412Z (2 months ago)
• Language: Python
• Size: 4.31 MB
• Stars: 14
• Watchers: 20
• Forks: 2
• Open Issues: 14
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Lists

• awesome-opensource-hardware - lake
• awesome-stars - StanfordAHA/lake - Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros. (Python)
• awesome-opensource-hardware-repos - lake

README

        
# lake

lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros. lake also comprises a library of generalized hardware modules aimed at memory controller designs.

## Install

`git clone github.com/StanfordAHA/lake`

`cd lake && pip install -e .`

## Run a test

To run a test, you can simply generate the verilog and push through your favorite verilog simulator. Alternatively, lake uses the pytest framework for unit tests of constituent modules. These tests leverage [fault](https://github.com/leonardt/fault) and [verilator](https://www.veripool.org/wiki/verilator) for open source simulation. Tests should run and pass on Linux and MacOS.

## Documentation

Check out the [wiki](https://github.com/StanfordAHA/lake/wiki) of this github repo.