https://byuccl.github.io/spydrnet/

A flexible framework for analyzing and transforming FPGA netlists. Official repository.
https://byuccl.github.io/spydrnet/

cad circuit circuit-analysis circuit-design circuits computer-aided-design digital eda edif electronic-design-automation fpga fpgas hardware hardware-designs netlist netlist-parser netlists transformation transformations

Last synced: 3 months ago
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A flexible framework for analyzing and transforming FPGA netlists. Official repository.

• Host: GitHub
• URL: https://byuccl.github.io/spydrnet/
• Owner: byuccl
• License: bsd-3-clause
• Created: 2019-09-23T15:25:09.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2024-03-04T21:00:36.000Z (11 months ago)
• Last Synced: 2024-08-31T23:03:59.088Z (5 months ago)
• Topics: cad, circuit, circuit-analysis, circuit-design, circuits, computer-aided-design, digital, eda, edif, electronic-design-automation, fpga, fpgas, hardware, hardware-designs, netlist, netlist-parser, netlists, transformation, transformations
• Language: Python
• Homepage: https://byuccl.github.io/spydrnet
• Size: 46 MB
• Stars: 88
• Watchers: 14
• Forks: 21
• Open Issues: 44
• Metadata Files:
  • Readme: README.rst
  • Contributing: CONTRIBUTING.rst
  • License: LICENSE

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