https://chipsalliance.github.io/verible/

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/

analysis formatter hacktoberfest language-server-protocol lexer linter lsp-server parser productivity style-linter sv-lrm syntax-tree systemverilog systemverilog-developer systemverilog-parser verible yacc

Last synced: 14 days ago
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Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

• Host: GitHub
• URL: https://chipsalliance.github.io/verible/
• Owner: chipsalliance
• License: other
• Created: 2019-11-07T00:04:47.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2024-10-16T16:26:57.000Z (24 days ago)
• Last Synced: 2024-10-18T12:23:26.152Z (22 days ago)
• Topics: analysis, formatter, hacktoberfest, language-server-protocol, lexer, linter, lsp-server, parser, productivity, style-linter, sv-lrm, syntax-tree, systemverilog, systemverilog-developer, systemverilog-parser, verible, yacc
• Language: C++
• Homepage: https://chipsalliance.github.io/verible/
• Size: 11.1 MB
• Stars: 1,351
• Watchers: 48
• Forks: 206
• Open Issues: 493
• Metadata Files:
  • Readme: README.md
  • Contributing: CONTRIBUTING.md
  • License: LICENSE
  • Authors: AUTHORS

Awesome Lists containing this project

• awesome-hdl - verible - Verible provides a SystemVerilog parser, style-linter, and formatter. (HDL parsers)