https://github.com/1sand0s/ssp-master-and-slave-verilog-module

FSM based SPI/SSP Master and Slave Verilog Module
https://github.com/1sand0s/ssp-master-and-slave-verilog-module

fifo-buffer rtl verilog verilog-hdl

Last synced: about 7 hours ago
JSON representation

FSM based SPI/SSP Master and Slave Verilog Module

• Host: GitHub
• URL: https://github.com/1sand0s/ssp-master-and-slave-verilog-module
• Owner: 1sand0s
• Created: 2019-12-06T08:36:48.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2019-12-08T07:27:27.000Z (about 5 years ago)
• Last Synced: 2023-02-27T16:31:04.765Z (almost 2 years ago)
• Topics: fifo-buffer, rtl, verilog, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 4.88 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0

Awesome Lists containing this project