https://github.com/28ritu/alu

An ALU Design in Verilog
https://github.com/28ritu/alu

alu verilog waveform

Last synced: 19 days ago
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An ALU Design in Verilog

• Host: GitHub
• URL: https://github.com/28ritu/alu
• Owner: 28Ritu
• Created: 2017-12-24T07:20:52.000Z (about 7 years ago)
• Default Branch: master
• Last Pushed: 2017-12-24T07:22:32.000Z (about 7 years ago)
• Last Synced: 2024-11-05T10:26:49.892Z (2 months ago)
• Topics: alu, verilog, waveform
• Language: Verilog
• Size: 89.8 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# ALU

An ALU Design in Verilog