https://github.com/64/eepyu
4-stage pipelined RISC-V CPU, written in SpinalHDL.
https://github.com/64/eepyu
Last synced: 26 days ago
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4-stage pipelined RISC-V CPU, written in SpinalHDL.
- Host: GitHub
- URL: https://github.com/64/eepyu
- Owner: 64
- License: mit
- Created: 2024-01-12T19:16:49.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2024-01-29T03:23:23.000Z (over 2 years ago)
- Last Synced: 2025-01-13T02:45:59.718Z (over 1 year ago)
- Language: Scala
- Homepage:
- Size: 65.4 KB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- License: LICENSE.md
Awesome Lists containing this project
- awesome-spinalhdl - eepyu - 4-stage pipelined RISC-V CPU (CPU)
README
# eepyu
eepyu (pronounced ee-pee-you) is a 4-stage pipelined CPU implementing the RISC-V base integer instruction set, implemented with [SpinalHDL](https://github.com/SpinalHDL/SpinalHDL).
It is optimised for area and *just about* fits on a ice40 HX1K FPGA (1280 LCs) running at 40-50 MHz.
## TODO
- RVFI RISC-V formal verification
- doit clean
- konata pipeline output
- optimise decoder signals