https://github.com/64/riscv-sim
Simulator for a high performance out-of-order RISC-V CPU.
https://github.com/64/riscv-sim
Last synced: over 1 year ago
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Simulator for a high performance out-of-order RISC-V CPU.
- Host: GitHub
- URL: https://github.com/64/riscv-sim
- Owner: 64
- License: mit
- Created: 2022-02-23T18:49:04.000Z (over 4 years ago)
- Default Branch: main
- Last Pushed: 2022-05-03T05:56:49.000Z (about 4 years ago)
- Last Synced: 2025-01-13T02:45:59.718Z (over 1 year ago)
- Language: Rust
- Homepage:
- Size: 145 KB
- Stars: 3
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: readme.txt
- License: LICENSE
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README
# CPU Cycle Simulator: UoB Advanced Computer Architecture
Requires a working Rust toolchain.
For tests, run `cargo test`.
To run an application `asm/foo.asm`, use `$ cargo run --release -- foo [param1] [param2]` where
`param1` and `param2` will be passed to the function in the A0 and A1 registers. If a path is
provided for one of these arguments, a file will be loaded to address 1000 with the contents.
Example:
```
$ cargo run --release -- prime 2946901
Compiling aca v0.1.0
Finished release [optimized] target(s) in 2.97s
Running `target/release/aca prime 2946901`
EXECUTION COMPLETED
=======================
R/S stalls: 2946853
Direct mispredicts: 0.00% (1/5893799)
Instructions retired: 11787603
Cycles taken: 5893808
Instructions per clock: 2.00
Simulator time elapsed: 9.74s (605 KHz)
EU utilisation:
Branch = 100%
LoadStore = 0%
Alu = 67%
Alu = 33%
```