https://github.com/Arlet/verilog-6502

A Verilog HDL model of the MOS 6502 CPU
https://github.com/Arlet/verilog-6502

Last synced: 2 months ago
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A Verilog HDL model of the MOS 6502 CPU

• Host: GitHub
• URL: https://github.com/Arlet/verilog-6502
• Owner: Arlet
• Created: 2011-05-02T17:01:23.000Z (over 13 years ago)
• Default Branch: master
• Last Pushed: 2023-04-08T07:12:30.000Z (almost 2 years ago)
• Last Synced: 2024-08-03T01:39:44.059Z (6 months ago)
• Language: Verilog
• Homepage: http://c-scape.nl/arlet/fpga/6502/
• Size: 20.5 KB
• Stars: 322
• Watchers: 30
• Forks: 92
• Open Issues: 2
• Metadata Files:
  • Readme: README.md

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README

        
A Verilog HDL version of the old MOS 6502 CPU.

Note: the 6502 core assumes a synchronous memory. This means that valid

data (DI) is expected on the cycle *after* valid address. This allows

direct connection to (Xilinx) block RAMs. When using asynchronous memory,

I suggest registering the address/control lines for glitchless output signals.

Have fun.