https://github.com/BrianHGinc/BrianHG-DDR3-Controller
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
https://github.com/BrianHGinc/BrianHG-DDR3-Controller
altera ddr3 fpga hdl intel lattice systemverilog testbenches verilog xilinx
Last synced: 4 months ago
JSON representation
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
- Host: GitHub
- URL: https://github.com/BrianHGinc/BrianHG-DDR3-Controller
- Owner: BrianHGinc
- Created: 2021-08-29T01:50:59.000Z (about 4 years ago)
- Default Branch: main
- Last Pushed: 2024-04-08T18:47:00.000Z (over 1 year ago)
- Last Synced: 2024-06-17T15:52:02.169Z (over 1 year ago)
- Topics: altera, ddr3, fpga, hdl, intel, lattice, systemverilog, testbenches, verilog, xilinx
- Language: SystemVerilog
- Homepage:
- Size: 9.94 MB
- Stars: 68
- Watchers: 6
- Forks: 29
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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